andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 

The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This commit is contained in:
Soby Mathew 2019-05-01 09:43:18 +01:00
parent 8917380a1e
commit e6e1d0ac16
4 changed files with 167 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
docs/cpu-specific-build-macros.rst
View File

@ -217,6 +217,18 @@ For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
DSU Errata Workarounds
----------------------

8
include/lib/cpus/aarch64/cortex_a76.h
View File

@ -19,6 +19,7 @@
#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
@ -27,10 +28,17 @@
#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)

116
lib/cpus/aarch64/cortex_a76.S
View File

@ -208,7 +208,7 @@ func errata_a76_1073348_wa
isb
1:
ret x17
endfunc errata_a76_1073348_wa
endfunc errata_a76_1073348_wa
func check_errata_1073348
mov x1, #0x10
@ -271,6 +271,101 @@ func check_errata_1220197
b cpu_rev_var_ls
endfunc check_errata_1220197
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1257314.
* This applies only to revision <= r3p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1257314_wa
/*
* Compare x0 against revision r3p0
*/
mov x17, x30
bl check_errata_1257314
cbz x0, 1f
mrs x1, CORTEX_A76_CPUACTLR3_EL1
orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
msr CORTEX_A76_CPUACTLR3_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1257314_wa
func check_errata_1257314
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1257314
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1262888.
* This applies only to revision <= r3p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1262888_wa
/*
* Compare x0 against revision r3p0
*/
mov x17, x30
bl check_errata_1262888
cbz x0, 1f
mrs x1, CORTEX_A76_CPUECTLR_EL1
orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
msr CORTEX_A76_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1262888_wa
func check_errata_1262888
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1262888
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1275112
* and Errata #1262606.
* This applies only to revision <= r3p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1275112_1262606_wa
/*
* Compare x0 against revision r3p0
*/
mov x17, x30
/*
* Since both errata #1275112 and #1262606 have the same check, we can
* invoke any one of them for the check here.
*/
bl check_errata_1275112
cbz x0, 1f
mrs x1, CORTEX_A76_CPUACTLR_EL1
orr x1, x1, CORTEX_A76_CPUACTLR_EL1_BIT_13
msr CORTEX_A76_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1275112_1262606_wa
func check_errata_1262606
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1262606
func check_errata_1275112
mov x1, #0x30
b cpu_rev_var_ls
endfunc check_errata_1275112
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
@ -313,6 +408,21 @@ func cortex_a76_reset_func
bl errata_a76_1220197_wa
#endif
#if ERRATA_A76_1257314
mov x0, x18
bl errata_a76_1257314_wa
#endif
#if ERRATA_A76_1262606 || ERRATA_A76_1275112
mov x0, x18
bl errata_a76_1275112_1262606_wa
#endif
#if ERRATA_A76_1262888
mov x0, x18
bl errata_a76_1262888_wa
#endif
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
mrs x0, id_aa64pfr1_el1
@ -388,6 +498,10 @@ func cortex_a76_errata_report
report_errata ERRATA_A76_1073348, cortex_a76, 1073348
report_errata ERRATA_A76_1130799, cortex_a76, 1130799
report_errata ERRATA_A76_1220197, cortex_a76, 1220197
report_errata ERRATA_A76_1257314, cortex_a76, 1257314
report_errata ERRATA_A76_1262606, cortex_a76, 1262606
report_errata ERRATA_A76_1262888, cortex_a76, 1262888
report_errata ERRATA_A76_1275112, cortex_a76, 1275112
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184

32
lib/cpus/cpu-ops.mk
View File

@ -210,6 +210,22 @@ ERRATA_A76_1130799 ?=0
# only to revision <= r2p0 of the Cortex A76 cpu.
ERRATA_A76_1220197 ?=0
# Flag to apply erratum 1257314 workaround during reset. This erratum applies
# only to revision <= r3p0 of the Cortex A76 cpu.
ERRATA_A76_1257314 ?=0
# Flag to apply erratum 1262606 workaround during reset. This erratum applies
# only to revision <= r3p0 of the Cortex A76 cpu.
ERRATA_A76_1262606 ?=0
# Flag to apply erratum 1262888 workaround during reset. This erratum applies
# only to revision <= r3p0 of the Cortex A76 cpu.
ERRATA_A76_1262888 ?=0
# Flag to apply erratum 1275112 workaround during reset. This erratum applies
# only to revision <= r3p0 of the Cortex A76 cpu.
ERRATA_A76_1275112 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=1
@ -375,6 +391,22 @@ $(eval $(call add_define,ERRATA_A76_1130799))
$(eval $(call assert_boolean,ERRATA_A76_1220197))
$(eval $(call add_define,ERRATA_A76_1220197))
# Process ERRATA_A76_1257314 flag
$(eval $(call assert_boolean,ERRATA_A76_1257314))
$(eval $(call add_define,ERRATA_A76_1257314))
# Process ERRATA_A76_1262606 flag
$(eval $(call assert_boolean,ERRATA_A76_1262606))
$(eval $(call add_define,ERRATA_A76_1262606))
# Process ERRATA_A76_1262888 flag
$(eval $(call assert_boolean,ERRATA_A76_1262888))
$(eval $(call add_define,ERRATA_A76_1262888))
# Process ERRATA_A76_1275112 flag
$(eval $(call assert_boolean,ERRATA_A76_1275112))
$(eval $(call add_define,ERRATA_A76_1275112))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))