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plat: intel: Add FPGAINTF configuration to when configuring pinmux 

FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
This commit is contained in:
Tien Hock Loh 2020-05-11 01:11:48 -07:00 committed by Manish Pandey
parent aea772dd7a
commit e734ecd61d
2 changed files with 10 additions and 0 deletions
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8
plat/intel/soc/agilex/soc/agilex_pinmux.c
View File

@ -7,6 +7,7 @@
#include <lib/mmio.h>
#include "agilex_pinmux.h"
#include "socfpga_system_manager.h"
const uint32_t sysmgr_pinmux_array_sel[] = {
0x00000000, 0x00000001, /* usb */
@ -185,6 +186,12 @@ const uint32_t sysmgr_pinmux_array_iodelay[] = {
0x0000011c, 0x00000000
};
void config_fpgaintf_mod(void)
{
mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
}
void config_pinmux(handoff *hoff_ptr)
{
unsigned int i;
@ -213,5 +220,6 @@ void config_pinmux(handoff *hoff_ptr)
hoff_ptr->pinmux_iodelay_array[i+1]);
}
config_fpgaintf_mod();
}

2
plat/intel/soc/common/include/socfpga_system_manager.h
View File

@ -13,6 +13,8 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
#define SOCFPGA_SYSMGR_EMAC_0 0x44
#define SOCFPGA_SYSMGR_EMAC_1 0x48
#define SOCFPGA_SYSMGR_EMAC_2 0x4c