fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8] to 1 which disables store issue prefetching. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
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Bipin Ravi
parent
0586c41b3f
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e7ca4433fa
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@ -454,6 +454,10 @@ For Cortex-X2, the following errata build flags are defined :
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- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
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CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
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- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
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Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
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r2p0 of the CPU, it is fixed in r2p1.
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DSU Errata Workarounds
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----------------------
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -13,6 +13,7 @@
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Extended Control register 2 specific definitions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -113,6 +113,34 @@ func check_errata_2083908
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b cpu_rev_var_range
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endfunc check_errata_2083908
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/* --------------------------------------------------
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* Errata Workaround for Cortex-X2 Errata 2017096.
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* This applies only to revisions r0p0, r1p0 and r2p0
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* and is fixed in r2p1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_x2_2017096_wa
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/* Compare x0 against revision r0p0 to r2p0 */
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mov x17, x30
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bl check_errata_2017096
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cbz x0, 1f
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mrs x1, CORTEX_X2_CPUECTLR_EL1
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orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
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msr CORTEX_X2_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_x2_2017096_wa
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func check_errata_2017096
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/* Applies to r0p0, r1p0, r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2017096
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -146,6 +174,7 @@ func cortex_x2_errata_report
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report_errata ERRATA_X2_2002765, cortex_x2, 2002765
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report_errata ERRATA_X2_2058056, cortex_x2, 2058056
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report_errata ERRATA_X2_2083908, cortex_x2, 2083908
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report_errata ERRATA_X2_2017096, cortex_x2, 2017096
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ldp x8, x30, [sp], #16
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ret
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@ -178,6 +207,11 @@ func cortex_x2_reset_func
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bl errata_cortex_x2_2083908_wa
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#endif
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#if ERRATA_X2_2017096
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mov x0, x18
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bl errata_x2_2017096_wa
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#endif
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ret x19
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endfunc cortex_x2_reset_func
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -497,15 +497,20 @@ ERRATA_A710_2017096 ?=0
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# Flag to apply erratum 2002765 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
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ERRATA_X2_2002765 ?=0
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ERRATA_X2_2002765 ?=0
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# Flag to apply erratum 2058056 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
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ERRATA_X2_2058056 ?=0
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ERRATA_X2_2058056 ?=0
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# Flag to apply erratum 2083908 workaround during reset. This erratum applies
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# to revision r2p0 of the Cortex-X2 cpu and is still open.
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ERRATA_X2_2083908 ?=0
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ERRATA_X2_2083908 ?=0
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# Flag to apply erratum 2017096 workaround during reset. This erratum applies
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# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
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# r2p1.
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ERRATA_X2_2017096 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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@ -944,6 +949,10 @@ $(eval $(call add_define,ERRATA_X2_2058056))
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$(eval $(call assert_boolean,ERRATA_X2_2083908))
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$(eval $(call add_define,ERRATA_X2_2083908))
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# Process ERRATA_X2_2017096 flag
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$(eval $(call assert_boolean,ERRATA_X2_2017096))
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$(eval $(call add_define,ERRATA_X2_2017096))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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