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fix(fvp): extend memory map to include all DRAM memory regions 

Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.

FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.

Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
This commit is contained in:
Federico Recanati 2021-12-23 11:01:11 +01:00
parent b22f18e365
commit e80354212f
2 changed files with 36 additions and 4 deletions
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20
plat/arm/board/fvp/fvp_security.c
View File

@ -1,11 +1,12 @@
/*
* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/arm_config.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
/*
* We assume that all security programming is done by the primary core.
@ -21,6 +22,21 @@ void plat_arm_security_setup(void)
* configurations, those would be configured here.
*/
const arm_tzc_regions_info_t fvp_tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
#if !SPM_MM && !ENABLE_RME
{FVP_DRAM3_BASE, FVP_DRAM3_END,
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
{FVP_DRAM4_BASE, FVP_DRAM4_END,
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
{FVP_DRAM5_BASE, FVP_DRAM5_END,
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
{FVP_DRAM6_BASE, FVP_DRAM6_END,
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS},
#endif
{0}
};
if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
arm_tzc400_setup(PLAT_ARM_TZC_BASE, fvp_tzc_regions);
}

20
plat/arm/board/fvp/include/platform_def.h
View File

@ -63,8 +63,24 @@
/* No SCP in FVP */
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */
#define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */
#define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */
#define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */
#define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U)
#define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */
#define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */
#define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U)
#define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */
#define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */
#define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U)
#define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */
#define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */
#define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U)
/* Range of kernel DTB load address */
#define FVP_DTB_DRAM_MAP_START ULL(0x82000000)