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plat: marvell: a8k: move address config of cp1/2 to BL2 

The configuration space of each standalone CP was updated in BL31.
Loading FW procedure take places earlier in SCP_BL2.
It needs to be done after access to each CP is provided.
Moving the proper configuration from BL31 to BL2 solves it.

Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea
Signed-off-by: Ben Peled <bpeled@marvell.com>
This commit is contained in:
Ben Peled 2019-03-26 19:06:24 +02:00 committed by Marcin Wojtas
parent cdfbbfefcb
commit e825176f1c
2 changed files with 10 additions and 15 deletions
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16
plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
View File

@ -10,6 +10,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/marvell/ccu.h>
#include <drivers/marvell/mochi/ap_setup.h>
#include <drivers/marvell/mochi/cp110_setup.h>
#include <lib/mmio.h>
@ -18,9 +19,6 @@
#include "mss_scp_bootloader.h"
/* IO windows configuration */
#define IOW_GCR_OFFSET (0x70)
/* MSS windows configuration */
#define MSS_AEBR(base) (base + 0x160)
#define MSS_AIBR(base) (base + 0x164)
@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
*/
static int bl2_plat_mmap_init(void)
{
int cfg_num, win_id, cfg_idx;
int cfg_num, win_id, cfg_idx, cp;
cfg_num = ARRAY_SIZE(ccu_mem_map);
@ -71,8 +69,14 @@ static int bl2_plat_mmap_init(void)
ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
}
/* Set the default target id to PIDI */
mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
/* Config address for each cp other than cp0 */
for (cp = 1; cp < CP_COUNT; cp++)
update_cp110_default_win(cp);
/* There is need to configure IO_WIN windows again to overwrite
* temporary configuration done during update_cp110_default_win
*/
init_io_win(MVEBU_AP0);
/* Open AMB bridge required for MG access */
for (cp = 0; cp < CP_COUNT; cp++)

9
plat/marvell/armada/a8k/common/plat_bl31_setup.c
View File

@ -116,21 +116,12 @@ void bl31_plat_arch_setup(void)
marvell_bl31_plat_arch_setup();
for (cp = 0; cp < CP_COUNT; cp++) {
if (cp >= 1)
update_cp110_default_win(cp);
cp110_init(MVEBU_CP_REGS_BASE(cp),
STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
marvell_bl31_mpp_init(cp);
}
/*
* There is need to configure IO_WIN windows again to overwrite
* temporary configuration done during update_cp110_default_win
*/
init_io_win(MVEBU_AP0);
for (cp = 1; cp < CP_COUNT; cp++)
mci_link_tune(cp - 1);