plat: marvell: a8k: move address config of cp1/2 to BL2
The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com>
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@ -10,6 +10,7 @@
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#include <common/bl_common.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/debug.h>
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/ccu.h>
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#include <drivers/marvell/mochi/ap_setup.h>
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#include <drivers/marvell/mochi/cp110_setup.h>
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#include <drivers/marvell/mochi/cp110_setup.h>
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#include <lib/mmio.h>
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#include <lib/mmio.h>
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@ -18,9 +19,6 @@
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#include "mss_scp_bootloader.h"
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#include "mss_scp_bootloader.h"
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/* IO windows configuration */
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#define IOW_GCR_OFFSET (0x70)
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/* MSS windows configuration */
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/* MSS windows configuration */
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#define MSS_AEBR(base) (base + 0x160)
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#define MSS_AEBR(base) (base + 0x160)
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#define MSS_AIBR(base) (base + 0x164)
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#define MSS_AIBR(base) (base + 0x164)
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@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
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*/
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*/
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static int bl2_plat_mmap_init(void)
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static int bl2_plat_mmap_init(void)
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{
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{
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int cfg_num, win_id, cfg_idx;
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int cfg_num, win_id, cfg_idx, cp;
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cfg_num = ARRAY_SIZE(ccu_mem_map);
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cfg_num = ARRAY_SIZE(ccu_mem_map);
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@ -71,8 +69,14 @@ static int bl2_plat_mmap_init(void)
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ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
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ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
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}
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}
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/* Set the default target id to PIDI */
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/* Config address for each cp other than cp0 */
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mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
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for (cp = 1; cp < CP_COUNT; cp++)
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update_cp110_default_win(cp);
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/* There is need to configure IO_WIN windows again to overwrite
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* temporary configuration done during update_cp110_default_win
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*/
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init_io_win(MVEBU_AP0);
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/* Open AMB bridge required for MG access */
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/* Open AMB bridge required for MG access */
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for (cp = 0; cp < CP_COUNT; cp++)
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for (cp = 0; cp < CP_COUNT; cp++)
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@ -116,21 +116,12 @@ void bl31_plat_arch_setup(void)
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marvell_bl31_plat_arch_setup();
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marvell_bl31_plat_arch_setup();
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for (cp = 0; cp < CP_COUNT; cp++) {
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for (cp = 0; cp < CP_COUNT; cp++) {
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if (cp >= 1)
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update_cp110_default_win(cp);
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cp110_init(MVEBU_CP_REGS_BASE(cp),
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cp110_init(MVEBU_CP_REGS_BASE(cp),
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STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
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STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
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marvell_bl31_mpp_init(cp);
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marvell_bl31_mpp_init(cp);
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}
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}
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/*
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* There is need to configure IO_WIN windows again to overwrite
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* temporary configuration done during update_cp110_default_win
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*/
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init_io_win(MVEBU_AP0);
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for (cp = 1; cp < CP_COUNT; cp++)
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for (cp = 1; cp < CP_COUNT; cp++)
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mci_link_tune(cp - 1);
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mci_link_tune(cp - 1);
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