Cortex-A76: fix spelling
Change-Id: I6adf7c14e8a974a7d40d51615b5e69eab1a7436f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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@ -22,11 +22,11 @@
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/*
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* This macro applies the mitigation for CVE-2018-3639.
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* It implements a fash path where `SMCCC_ARCH_WORKAROUND_2`
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* It implements a fast path where `SMCCC_ARCH_WORKAROUND_2`
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* SMC calls from a lower EL running in AArch32 or AArch64
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* will go through the fast and return early.
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*
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* The macro saves x2-x3 to the context. In the fast path
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* The macro saves x2-x3 to the context. In the fast path
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* x0-x3 registers do not need to be restored as the calling
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* context will have saved them.
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*/
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@ -63,7 +63,7 @@
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* When the calling context wants mitigation disabled,
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* we program the mitigation disable function in the
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* CPU context, which gets invoked on subsequent exits from
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* EL3 via the `el3_exit` function. Otherwise NULL is
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* EL3 via the `el3_exit` function. Otherwise NULL is
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* programmed in the CPU context, which results in caller's
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* inheriting the EL3 mitigation state (enabled) on subsequent
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* `el3_exit`.
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@ -82,7 +82,7 @@
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.endif
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1:
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/*
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* Always enable v4 mitigation during EL3 execution. This is not
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* Always enable v4 mitigation during EL3 execution. This is not
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* required for the fast path above because it does not perform any
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* memory loads.
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*/
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@ -319,7 +319,7 @@ func cortex_a76_reset_func
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/* If the PE implements SSBS, we don't need the dynamic workaround */
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mrs x0, id_aa64pfr1_el1
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lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT
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and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK
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and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK
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cbnz x0, 1f
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mrs x0, CORTEX_A76_CPUACTLR2_EL1
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@ -330,7 +330,7 @@ func cortex_a76_reset_func
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#ifdef IMAGE_BL31
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/*
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* The Cortex-A76 generic vectors are overwritten to use the vectors
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* defined above. This is required in order to apply mitigation
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* defined above. This is required in order to apply mitigation
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* against CVE-2018-3639 on exception entry from lower ELs.
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*/
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adr x0, cortex_a76_wa_cve_2018_3639_a76_vbar
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