Automatically select initial xlation lookup level
Instead of hardcoding a level 1 table as the base translation level table, let the code decide which level is the most appropriate given the virtual address space size. As the table granularity is 4 KB, this allows the code to select level 0, 1 or 2 as base level for AArch64. This way, instead of limiting the virtual address space width to 39-31 bits, widths of 48-25 bit can be used. For AArch32, this change allows the code to select level 1 or 2 as the base translation level table and use virtual address space width of 32-25 bits. Also removed some unused definitions related to translation tables. Fixes ARM-software/tf-issues#362 Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
This commit is contained in:
Antonio Nino Diaz
Soby Mathew
parent
079e522d39
commit
e8719552a2
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@ -254,6 +254,8 @@
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#define TTBCR_T1SZ_SHIFT 16
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#define TTBCR_T1SZ_MASK (0x7)
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#define TTBCR_TxSZ_MIN 0
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#define TTBCR_TxSZ_MAX 7
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#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
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#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
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@ -243,6 +243,9 @@
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#define TCR_EL1_IPS_SHIFT 32
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#define TCR_EL3_PS_SHIFT 16
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#define TCR_TxSZ_MIN 16
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#define TCR_TxSZ_MAX 39
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/* (internal) physical address size bits in EL3/EL1 */
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#define TCR_PS_BITS_4GB (0x0)
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#define TCR_PS_BITS_64GB (0x1)
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@ -32,29 +32,12 @@
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#define __XLAT_TABLES_H__
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (1 << 9)
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#define NUM_4K_IN_2MB (1 << 9)
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#define NUM_GB_IN_4GB (1 << 2)
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#define TWO_MB_SHIFT 21
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#define ONE_GB_SHIFT 30
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#define FOUR_KB_SHIFT 12
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define INVALID_DESC 0x0
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#define BLOCK_DESC 0x1
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#define TABLE_DESC 0x3
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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#define LEVEL1 1
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#define LEVEL2 2
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#define LEVEL3 3
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#define BLOCK_DESC 0x1 /* Table levels 0-2 */
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#define TABLE_DESC 0x3 /* Table levels 0-2 */
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#define PAGE_DESC 0x3 /* Table level 3 */
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#define XN (1ull << 2)
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#define PXN (1ull << 1)
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@ -78,6 +61,14 @@
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
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#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
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#ifdef AARCH32
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#define XLAT_TABLE_LEVEL_MIN 1
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#else
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#define XLAT_TABLE_LEVEL_MIN 0
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#endif /* AARCH32 */
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#define XLAT_TABLE_LEVEL_MAX 3
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/* Values for number of entries in each MMU translation table */
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#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
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@ -87,6 +78,7 @@
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#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
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#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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/*
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* AP[1] bit is ignored by hardware and is
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@ -38,25 +38,57 @@
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#include "../xlat_tables_private.h"
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/*
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* The virtual address space size must be a power of two. As we start the initial
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* lookup at level 1, it must also be between 2 GB and 4 GB. See section
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* G4.6.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information.
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* Each platform can define the size of the virtual address space, which is
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* defined in ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus the width
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* of said address space. The value of TTBCR.TxSZ must be in the range 0 to
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* 7 [1], which means that the virtual address space width must be in the range
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* 32 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE.
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* For a 4 KB page size, level 1 supports virtual address spaces of widths 32
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* to 31 bits, and level 2 from 30 to 25. Wider or narrower address spaces are
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* not supported. As a result, level 3 cannot be used as initial lookup level
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* with 4 KB granularity [1].
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*
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* For example, for a 31-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 31),
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* TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table G4-5 in
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* the ARM ARM, the initial lookup level for such an address space is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Section G4.6.5
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*/
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CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 32) &&
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IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
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#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#if ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN))
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static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
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__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
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# error "ADDR_SPACE_SIZE is too big."
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#elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "ADDR_SPACE_SIZE is too small."
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#endif
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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print_mmap();
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init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa);
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init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va < ADDR_SPACE_SIZE);
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}
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@ -95,7 +127,7 @@ void enable_mmu_secure(unsigned int flags)
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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ttbr0 = (uintptr_t) l1_xlation_table;
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ttbr0 = (uintptr_t) base_xlation_table;
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write64_ttbr0(ttbr0);
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write64_ttbr1(0);
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@ -38,19 +38,55 @@
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#include "../xlat_tables_private.h"
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/*
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* The virtual address space size must be a power of two (as set in TCR.T0SZ).
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* As we start the initial lookup at level 1, it must also be between 2 GB and
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* 512 GB (with the virtual address size therefore 31 to 39 bits). See section
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* D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.i) for more
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* information.
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* Each platform can define the size of the virtual address space, which is
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* defined in ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the width of
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* said address space. The value of TCR.TxSZ must be in the range 16 to 39 [1],
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* which means that the virtual address space width must be in the range 48 to
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* 25 bits.
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*
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* Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE.
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* For a 4 KB page size, level 0 supports virtual address spaces of widths 48 to
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* 40 bits, level 1 from 39 to 31, and level 2 from 30 to 25. Wider or narrower
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* address spaces are not supported. As a result, level 3 cannot be used as
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* initial lookup level with 4 KB granularity. [2]
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*
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* For example, for a 35-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 35),
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* TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table D4-11 in
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* the ARM ARM, the initial lookup level for such an address space is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Page 1730: 'Input address size', 'For all translation stages'.
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* [2] Section D4.2.5
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*/
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CASSERT(ADDR_SPACE_SIZE >= (1ull << 31) && ADDR_SPACE_SIZE <= (1ull << 39) &&
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IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
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#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#if ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
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static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
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__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
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# error "ADDR_SPACE_SIZE is too big."
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#elif ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 0
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
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#elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "ADDR_SPACE_SIZE is too small."
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#endif
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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static unsigned long long tcr_ps_bits;
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@ -88,7 +124,8 @@ void init_xlat_tables(void)
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unsigned long long max_pa;
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uintptr_t max_va;
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print_mmap();
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init_xlation_table(0, l1_xlation_table, 1, &max_va, &max_pa);
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init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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assert(max_va < ADDR_SPACE_SIZE);
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}
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@ -124,7 +161,8 @@ void init_xlat_tables(void)
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_tlbi_fct(); \
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\
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/* Set TCR bits as well. */ \
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/* Inner & outer WBWA & shareable + T0SZ = 32 */ \
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/* Inner & outer WBWA & shareable. */ \
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/* Set T0SZ to (64 - width of virtual address space) */ \
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
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TCR_RGN_INNER_WBA | \
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(64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \
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@ -132,7 +170,7 @@ void init_xlat_tables(void)
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) l1_xlation_table; \
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ttbr = (uint64_t) base_xlation_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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@ -199,7 +199,11 @@ static uint64_t mmap_desc(unsigned attr, unsigned long long addr_pa,
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int mem_type;
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desc = addr_pa;
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desc |= (level == 3) ? TABLE_DESC : BLOCK_DESC;
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/*
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* There are different translation table descriptors for level 3 and the
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* rest.
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*/
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desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC;
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desc |= (attr & MT_NS) ? LOWER_ATTRS(NS) : 0;
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desc |= (attr & MT_RW) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
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desc |= LOWER_ATTRS(ACCESS_FLAG);
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@ -311,14 +315,13 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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uint64_t *table,
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int level)
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{
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unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) *
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XLAT_TABLE_ENTRIES_SHIFT;
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unsigned level_size = 1 << level_size_shift;
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u_register_t level_index_mask =
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(u_register_t)(((u_register_t) XLAT_TABLE_ENTRIES_MASK)
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<< level_size_shift);
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assert(level >= XLAT_TABLE_LEVEL_MIN && level <= XLAT_TABLE_LEVEL_MAX);
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assert(level > 0 && level <= 3);
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unsigned int level_size_shift =
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L0_XLAT_ADDRESS_SHIFT - level * XLAT_TABLE_ENTRIES_SHIFT;
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u_register_t level_size = (u_register_t)1 << level_size_shift;
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u_register_t level_index_mask =
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((u_register_t)XLAT_TABLE_ENTRIES_MASK) << level_size_shift;
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debug_print("New xlat table:\n");
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@ -334,8 +337,8 @@ static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm,
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continue;
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}
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debug_print("%s VA:%p size:0x%x ", get_level_spacer(level),
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(void *)base_va, level_size);
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debug_print("%s VA:%p size:0x%llx ", get_level_spacer(level),
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(void *)base_va, (unsigned long long)level_size);
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if (mm->base_va > base_va + level_size - 1) {
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/* Next region is after this area. Nothing to map yet */
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@ -31,6 +31,12 @@
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#ifndef __XLAT_TABLES_PRIVATE_H__
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#define __XLAT_TABLES_PRIVATE_H__
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#include <cassert.h>
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#include <utils.h>
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/* The virtual address space size must be a power of two. */
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CASSERT(IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size);
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void print_mmap(void);
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void init_xlation_table(uintptr_t base_va, uint64_t *table,
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int level, uintptr_t *max_va,
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