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Merge changes from topic "stm32_drivers_update" into integration 

* changes:
  clk: stm32mp1: fix rcc mckprot status
  drivers: st: add missing includes in ETZPC header
  mmc: st: clear some flags before sending a command
  mmc: st: correct retries management
  nand: raw_nand: fix timeout issue in nand_wait_ready
  mtd: spi_nor: change message level on macronix detection
  gpio: stm32_gpio: check GPIO node status after checking DT
  crypto: stm32_hash: fix issue when restarting computation
This commit is contained in:
Manish Pandey 2020-09-25 08:30:53 +00:00 committed by TrustedFirmware Code Review
parent 6b745042ea 1bb9072ab4
commit e89b813129
9 changed files with 53 additions and 26 deletions
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6
drivers/mtd/nand/raw_nand.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -190,7 +190,7 @@ static int nand_status(uint8_t *status)
return ret;
}
int nand_wait_ready(unsigned long delay)
int nand_wait_ready(unsigned int delay_ms)
{
uint8_t status;
int ret;
@ -204,7 +204,7 @@ int nand_wait_ready(unsigned long delay)
return ret;
}
timeout = timeout_init_us(delay);
timeout = timeout_init_us(delay_ms * 1000U);
while (!timeout_elapsed(timeout)) {
ret = nand_read_data(&status, 1U, true);
if (ret != 0) {

4
drivers/mtd/nor/spi_nor.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -368,7 +368,7 @@ int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
if (nor_dev.read_op.data.buswidth == 4U) {
switch (id) {
case MACRONIX_ID:
WARN("Enable Macronix quad support\n");
INFO("Enable Macronix quad support\n");
ret = spi_nor_macronix_quad_enable();
break;
case MICRON_ID:

6
drivers/st/clk/stm32mp1_clk.c
View File

@ -653,15 +653,17 @@ static void stm32mp1_clk_unlock(struct spinlock *lock)
bool stm32mp1_rcc_is_secure(void)
{
uintptr_t rcc_base = stm32mp_rcc_base();
uint32_t mask = RCC_TZCR_TZEN;
return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0;
return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
}
bool stm32mp1_rcc_is_mckprot(void)
{
uintptr_t rcc_base = stm32mp_rcc_base();
uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT;
return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0;
return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
}
void stm32mp1_clk_rcc_regs_lock(void)

4
drivers/st/crypto/stm32_hash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -252,6 +252,8 @@ int stm32_hash_final(uint8_t *digest)
mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK,
8U * stm32_remain.length);
zeromem(&stm32_remain, sizeof(stm32_remain));
} else {
mmio_clrbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK);
}
mmio_setbits_32(hash_base() + HASH_STR, HASH_STR_DCAL);

5
drivers/st/gpio/stm32_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -161,13 +161,14 @@ int dt_set_pinctrl_config(int node)
const fdt32_t *cuint;
int lenp = 0;
uint32_t i;
uint8_t status = fdt_get_status(node);
uint8_t status;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -FDT_ERR_NOTFOUND;
}
status = fdt_get_status(node);
if (status == DT_DISABLED) {
return -FDT_ERR_NOTFOUND;
}

19
drivers/st/io/io_mmc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -97,14 +97,21 @@ static int mmc_block_seek(io_entity_t *entity, int mode,
static int mmc_block_read(io_entity_t *entity, uintptr_t buffer,
size_t length, size_t *length_read)
{
*length_read = mmc_read_blocks(seek_offset / MMC_BLOCK_SIZE,
buffer, length);
uint8_t retries;
if (*length_read != length) {
return -EIO;
for (retries = 0U; retries < 3U; retries++) {
*length_read = mmc_read_blocks(seek_offset / MMC_BLOCK_SIZE,
buffer, length);
if (*length_read == length) {
return 0;
}
WARN("%s: length_read = %lu (!= %lu), retry %u\n", __func__,
(unsigned long)*length_read, (unsigned long)length,
retries + 1U);
}
return 0;
return -EIO;
}
/* Close a file on the mmc device */

30
drivers/st/mmc/stm32_sdmmc2.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -258,6 +258,18 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
break;
}
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
/*
* Clear the SDMMC_DCTRLR if the command does not await data.
* Skip CMD55 as the next command could be data related, and
* the register could have been set in prepare function.
*/
if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) &&
(cmd->cmd_idx != MMC_CMD(55))) {
mmio_write_32(base + SDMMC_DCTRLR, 0U);
}
if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
}
@ -373,15 +385,15 @@ err_exit:
static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
{
int8_t retry;
int err = 0;
uint8_t retry;
int err;
assert(cmd != NULL);
for (retry = 0; retry <= 3; retry++) {
for (retry = 0U; retry < 3U; retry++) {
err = stm32_sdmmc2_send_cmd_req(cmd);
if (err == 0) {
return err;
return 0;
}
if ((cmd->cmd_idx == MMC_CMD(1)) ||
@ -390,12 +402,12 @@ static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
}
/* Command 8 is expected to fail for eMMC */
if (!(cmd->cmd_idx == MMC_CMD(8))) {
WARN(" CMD%d, Retry: %d, Error: %d\n",
cmd->cmd_idx, retry, err);
if (cmd->cmd_idx != MMC_CMD(8)) {
WARN(" CMD%u, Retry: %u, Error: %d\n",
cmd->cmd_idx, retry + 1U, err);
}
udelay(10);
udelay(10U);
}
return err;

2
include/drivers/raw_nand.h
View File

@ -169,7 +169,7 @@ struct rawnand_device {
};
int nand_raw_init(unsigned long long *size, unsigned int *erase_size);
int nand_wait_ready(unsigned long delay);
int nand_wait_ready(unsigned int delay_ms);
int nand_read_page_cmd(unsigned int page, unsigned int offset,
uintptr_t buffer, unsigned int len);
int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer,

3
include/drivers/st/etzpc.h
View File

@ -7,6 +7,9 @@
#ifndef DRIVERS_ST_ETZPC_H
#define DRIVERS_ST_ETZPC_H
#include <stdbool.h>
#include <stdint.h>
/* Define security level for each peripheral (DECPROT) */
enum etzpc_decprot_attributes {
ETZPC_DECPROT_S_RW = 0,