Merge changes I46cd4d9b,Iba009587,I41d146e8,Ic66ceab3,Iff46838a, ... into integration
* changes: drivers: renesas: rcar: io: Code cleanup drivers: renesas: rcar: pwrc: Code cleanup drivers: renesas: rcar: common: Code cleanup drivers: renesas: rcar: watchdog: Fix typo drivers: renesas: rcar: scif: Fix coding style drivers: renesas: rcar: iic_dvfs: Fix coding style
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
e8a96e3e23
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,24 +8,27 @@
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#include "rcar_private.h"
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void
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#if IMAGE_BL31
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__attribute__ ((section(".system_ram")))
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void __attribute__ ((section(".system_ram"))) cpg_write(uintptr_t regadr, uint32_t regval)
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#else
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void cpg_write(uintptr_t regadr, uint32_t regval)
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#endif
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cpg_write(uintptr_t regadr, uint32_t regval)
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{
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uint32_t value = (regval);
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uint32_t value = regval;
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mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
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mmio_write_32(regadr, value);
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}
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void
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#if IMAGE_BL31
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__attribute__ ((section(".system_ram")))
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void __attribute__ ((section(".system_ram"))) mstpcr_write(uint32_t mstpcr, uint32_t mstpsr,
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uint32_t target_bit)
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#else
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void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
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#endif
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mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
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{
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uint32_t reg;
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reg = mmio_read_32(mstpcr);
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reg &= ~target_bit;
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cpg_write(mstpcr, reg);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,59 +7,59 @@
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "rcar_def.h"
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#include "cpg_registers.h"
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#include "iic_dvfs.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#define DVFS_RETRY_MAX (2U)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0B)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0E)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15U)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07U)
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#define CPG_BIT_SMSTPCR9_DVFS (0x04000000)
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#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U)
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#define IIC_DVFS_REG_BASE (0xE60B0000)
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#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000)
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#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004)
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#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008)
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#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000C)
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#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010)
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#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014)
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#define IIC_DVFS_REG_BASE (0xE60B0000U)
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#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U)
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#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U)
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#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U)
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#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU)
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#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U)
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#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U)
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#define IIC_DVFS_BIT_ICSR_BUSY (0x10)
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#define IIC_DVFS_BIT_ICSR_AL (0x08)
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#define IIC_DVFS_BIT_ICSR_TACK (0x04)
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#define IIC_DVFS_BIT_ICSR_WAIT (0x02)
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#define IIC_DVFS_BIT_ICSR_DTE (0x01)
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#define IIC_DVFS_BIT_ICSR_BUSY (0x10U)
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#define IIC_DVFS_BIT_ICSR_AL (0x08U)
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#define IIC_DVFS_BIT_ICSR_TACK (0x04U)
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#define IIC_DVFS_BIT_ICSR_WAIT (0x02U)
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#define IIC_DVFS_BIT_ICSR_DTE (0x01U)
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#define IIC_DVFS_BIT_ICCR_ENABLE (0x80)
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#define IIC_DVFS_SET_ICCR_START (0x94)
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#define IIC_DVFS_SET_ICCR_STOP (0x90)
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#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94)
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#define IIC_DVFS_SET_ICCR_CHANGE (0x81)
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#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0)
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#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U)
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#define IIC_DVFS_SET_ICCR_START (0x94U)
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#define IIC_DVFS_SET_ICCR_STOP (0x90U)
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#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U)
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#define IIC_DVFS_SET_ICCR_CHANGE (0x81U)
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#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U)
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#define IIC_DVFS_BIT_ICIC_TACKE (0x04)
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#define IIC_DVFS_BIT_ICIC_WAITE (0x02)
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#define IIC_DVFS_BIT_ICIC_DTEE (0x01)
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#define IIC_DVFS_BIT_ICIC_TACKE (0x04U)
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#define IIC_DVFS_BIT_ICIC_WAITE (0x02U)
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#define IIC_DVFS_BIT_ICIC_DTEE (0x01U)
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#define DVFS_READ_MODE (0x01)
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#define DVFS_WRITE_MODE (0x00)
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#define DVFS_READ_MODE (0x01U)
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#define DVFS_WRITE_MODE (0x00U)
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#define IIC_DVFS_SET_DUMMY (0x52)
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#define IIC_DVFS_SET_DUMMY (0x52U)
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#define IIC_DVFS_SET_BUSY_LOOP (500000000U)
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typedef enum {
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enum dvfs_state_t {
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DVFS_START = 0,
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DVFS_STOP,
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DVFS_RETRANSMIT,
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@ -69,9 +69,9 @@ typedef enum {
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DVFS_SET_SLAVE,
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DVFS_WRITE_ADDR,
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DVFS_WRITE_DATA,
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DVFS_CHANGE_SEND_TO_RECIEVE,
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DVFS_CHANGE_SEND_TO_RECEIVE,
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DVFS_DONE,
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} DVFS_STATE_T;
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};
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#define DVFS_PROCESS (1)
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#define DVFS_COMPLETE (0)
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@ -94,11 +94,11 @@ static int32_t dvfs_ ##__name(__VA_ARGS__)
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int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
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#endif
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IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
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IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode)
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{
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uint8_t icsr_al = 0, icsr_tack = 0;
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uint8_t icsr_al = 0U, icsr_tack = 0U;
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uint8_t reg, stop;
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uint32_t i = 0;
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uint32_t i = 0U;
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stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
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IIC_DVFS_SET_ICCR_STOP;
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@ -107,43 +107,48 @@ IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
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icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
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icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
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if (icsr_al == 0 && icsr_tack == 0)
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if (icsr_al == 0U && icsr_tack == 0U) {
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return DVFS_PROCESS;
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}
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if (icsr_al) {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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if (*state == DVFS_SET_SLAVE)
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if (*state == DVFS_SET_SLAVE) {
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mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
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}
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do {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
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IIC_DVFS_BIT_ICSR_WAIT;
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} while (reg == 0);
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} while (reg == 0U);
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mmio_write_8(IIC_DVFS_REG_ICCR, stop);
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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i = 0;
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i = 0U;
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do {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
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IIC_DVFS_BIT_ICSR_BUSY;
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if (reg == 0)
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if (reg == 0U) {
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break;
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}
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if (i++ > IIC_DVFS_SET_BUSY_LOOP)
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if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
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panic();
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}
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} while (1);
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} while (true);
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mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
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(*err)++;
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if (*err > DVFS_RETRY_MAX)
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if (*err > DVFS_RETRY_MAX) {
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return DVFS_ERROR;
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}
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*state = DVFS_START;
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@ -161,24 +166,26 @@ IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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i = 0;
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while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
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if (i++ > IIC_DVFS_SET_BUSY_LOOP)
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i = 0U;
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while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
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if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
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panic();
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}
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}
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mmio_write_8(IIC_DVFS_REG_ICCR, 0);
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mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
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(*err)++;
|
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|
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if (*err > DVFS_RETRY_MAX)
|
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if (*err > DVFS_RETRY_MAX) {
|
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return DVFS_ERROR;
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}
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*state = DVFS_START;
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return DVFS_PROCESS;
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}
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IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
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IIC_DVFS_FUNC(start, enum dvfs_state_t *state)
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{
|
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uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
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uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
|
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|
|
@ -190,8 +197,9 @@ IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
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mmio_write_8(IIC_DVFS_REG_ICCR, mode);
|
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|
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lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
|
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if (lsi_product == PRR_PRODUCT_E3)
|
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if (lsi_product == PRR_PRODUCT_E3) {
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goto start;
|
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}
|
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|
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reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
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switch (reg) {
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|
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@ -228,19 +236,21 @@ start:
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return result;
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}
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IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
|
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IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave)
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{
|
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uint8_t mode;
|
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int32_t result;
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uint8_t address;
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|
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
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if (result == DVFS_ERROR)
|
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if (result == DVFS_ERROR) {
|
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return result;
|
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}
|
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|
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
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if (mode != IIC_DVFS_BIT_ICSR_DTE)
|
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if (mode != IIC_DVFS_BIT_ICSR_DTE) {
|
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return result;
|
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}
|
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|
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mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
|
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mmio_write_8(IIC_DVFS_REG_ICIC, mode);
|
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|
|
@ -253,18 +263,20 @@ IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
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return result;
|
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}
|
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|
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IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
|
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IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr)
|
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{
|
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uint8_t mode;
|
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int32_t result;
|
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|
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
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if (result == DVFS_ERROR)
|
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if (result == DVFS_ERROR) {
|
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return result;
|
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}
|
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|
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
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if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
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return result;
|
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}
|
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|
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mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
|
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|
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|
|
@ -276,18 +288,21 @@ IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
|
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return result;
|
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}
|
||||
|
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IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
|
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IIC_DVFS_FUNC(write_data, enum dvfs_state_t *state, uint32_t *err,
|
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uint8_t reg_data)
|
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{
|
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int32_t result;
|
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uint8_t mode;
|
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|
||||
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
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return result;
|
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}
|
||||
|
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mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
|
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|
||||
|
|
@ -299,18 +314,20 @@ IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
|
|||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
|
||||
IIC_DVFS_FUNC(stop, enum dvfs_state_t *state, uint32_t *err)
|
||||
{
|
||||
int32_t result;
|
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uint8_t mode;
|
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|
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
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if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
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return result;
|
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}
|
||||
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
|
||||
|
||||
|
|
@ -326,32 +343,35 @@ IIC_DVFS_FUNC(done, void)
|
|||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
|
||||
if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
|
||||
for (i = 0U; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
|
||||
if ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
|
||||
continue;
|
||||
}
|
||||
goto done;
|
||||
}
|
||||
|
||||
panic();
|
||||
done:
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0);
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
|
||||
|
||||
return DVFS_COMPLETE;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
|
||||
IIC_DVFS_FUNC(write_reg_addr_read, enum dvfs_state_t *state, uint32_t *err,
|
||||
uint8_t reg_addr)
|
||||
{
|
||||
int32_t result;
|
||||
uint8_t mode;
|
||||
|
||||
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
|
||||
|
||||
|
|
@ -363,18 +383,20 @@ IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
|
|||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
|
||||
IIC_DVFS_FUNC(retransmit, enum dvfs_state_t *state, uint32_t *err)
|
||||
{
|
||||
int32_t result;
|
||||
uint8_t mode;
|
||||
|
||||
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
|
||||
|
||||
|
|
@ -389,7 +411,7 @@ IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
|
|||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
|
||||
IIC_DVFS_FUNC(set_slave_read, enum dvfs_state_t *state, uint32_t *err,
|
||||
uint8_t slave)
|
||||
{
|
||||
uint8_t address;
|
||||
|
|
@ -397,12 +419,14 @@ IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
|
|||
uint8_t mode;
|
||||
|
||||
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_DTE)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_DTE) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
|
||||
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
|
||||
|
|
@ -410,23 +434,25 @@ IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
|
|||
address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
|
||||
mmio_write_8(IIC_DVFS_REG_ICDR, address);
|
||||
|
||||
*state = DVFS_CHANGE_SEND_TO_RECIEVE;
|
||||
*state = DVFS_CHANGE_SEND_TO_RECEIVE;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
|
||||
IIC_DVFS_FUNC(change_send_to_receive, enum dvfs_state_t *state, uint32_t *err)
|
||||
{
|
||||
int32_t result;
|
||||
uint8_t mode;
|
||||
|
||||
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
|
||||
|
||||
|
|
@ -438,18 +464,20 @@ IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
|
|||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
|
||||
IIC_DVFS_FUNC(stop_read, enum dvfs_state_t *state, uint32_t *err)
|
||||
{
|
||||
int32_t result;
|
||||
uint8_t mode;
|
||||
|
||||
result = dvfs_check_error(state, err, DVFS_READ_MODE);
|
||||
if (result == DVFS_ERROR)
|
||||
if (result == DVFS_ERROR) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
|
||||
return result;
|
||||
}
|
||||
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
|
||||
|
||||
|
|
@ -464,13 +492,14 @@ IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
|
|||
return result;
|
||||
}
|
||||
|
||||
IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
|
||||
IIC_DVFS_FUNC(read, enum dvfs_state_t *state, uint8_t *reg_data)
|
||||
{
|
||||
uint8_t mode;
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
|
||||
if (mode != IIC_DVFS_BIT_ICSR_DTE)
|
||||
if (mode != IIC_DVFS_BIT_ICSR_DTE) {
|
||||
return DVFS_PROCESS;
|
||||
}
|
||||
|
||||
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
|
||||
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
|
||||
|
|
@ -483,12 +512,12 @@ IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
|
|||
|
||||
RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
|
||||
{
|
||||
DVFS_STATE_T state = DVFS_START;
|
||||
enum dvfs_state_t state = DVFS_START;
|
||||
int32_t result = DVFS_PROCESS;
|
||||
uint32_t err = 0;
|
||||
uint32_t err = 0U;
|
||||
|
||||
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0);
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
|
||||
again:
|
||||
switch (state) {
|
||||
case DVFS_START:
|
||||
|
|
@ -514,20 +543,21 @@ again:
|
|||
break;
|
||||
}
|
||||
|
||||
if (result == DVFS_PROCESS)
|
||||
if (result == DVFS_PROCESS) {
|
||||
goto again;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
|
||||
{
|
||||
DVFS_STATE_T state = DVFS_START;
|
||||
enum dvfs_state_t state = DVFS_START;
|
||||
int32_t result = DVFS_PROCESS;
|
||||
uint32_t err = 0;
|
||||
uint32_t err = 0U;
|
||||
|
||||
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0);
|
||||
mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
|
||||
again:
|
||||
switch (state) {
|
||||
case DVFS_START:
|
||||
|
|
@ -545,8 +575,8 @@ again:
|
|||
case DVFS_SET_SLAVE_READ:
|
||||
result = dvfs_set_slave_read(&state, &err, slave);
|
||||
break;
|
||||
case DVFS_CHANGE_SEND_TO_RECIEVE:
|
||||
result = dvfs_change_send_to_recieve(&state, &err);
|
||||
case DVFS_CHANGE_SEND_TO_RECEIVE:
|
||||
result = dvfs_change_send_to_receive(&state, &err);
|
||||
break;
|
||||
case DVFS_STOP_READ:
|
||||
result = dvfs_stop_read(&state, &err);
|
||||
|
|
@ -562,8 +592,9 @@ again:
|
|||
break;
|
||||
}
|
||||
|
||||
if (result == DVFS_PROCESS)
|
||||
if (result == DVFS_PROCESS) {
|
||||
goto again;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -8,14 +8,14 @@
|
|||
#define IIC_DVFS_H
|
||||
|
||||
/* PMIC slave */
|
||||
#define PMIC (0x30)
|
||||
#define BKUP_MODE_CNT (0x20)
|
||||
#define DVFS_SET_VID (0x54)
|
||||
#define REG_KEEP10 (0x79)
|
||||
#define PMIC (0x30U)
|
||||
#define BKUP_MODE_CNT (0x20U)
|
||||
#define DVFS_SET_VID (0x54U)
|
||||
#define REG_KEEP10 (0x79U)
|
||||
|
||||
/* EEPROM slave */
|
||||
#define EEPROM (0x50)
|
||||
#define BOARD_ID (0x70)
|
||||
#define EEPROM (0x50U)
|
||||
#define BOARD_ID (0x70U)
|
||||
|
||||
int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
|
||||
int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -10,13 +10,13 @@
|
|||
#include <drivers/io/io_driver.h>
|
||||
#include <drivers/io/io_storage.h>
|
||||
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_def.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "io_common.h"
|
||||
#include "io_emmcdrv.h"
|
||||
#include "io_private.h"
|
||||
#include "emmc_config.h"
|
||||
#include "emmc_hal.h"
|
||||
#include "emmc_std.h"
|
||||
#include "emmc_def.h"
|
||||
|
||||
static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
|
||||
io_dev_info_t **dev_info);
|
||||
|
|
@ -41,8 +41,9 @@ static io_type_t device_type_emmcdrv(void)
|
|||
static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
|
||||
signed long long offset)
|
||||
{
|
||||
if (mode != IO_SEEK_SET)
|
||||
if (mode != IO_SEEK_SET) {
|
||||
return IO_FAIL;
|
||||
}
|
||||
|
||||
((file_state_t *) entity->info)->file_pos = offset;
|
||||
|
||||
|
|
@ -64,12 +65,14 @@ static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer,
|
|||
current_file.partition, current_file.file_pos,
|
||||
sector_add, length, sector_num);
|
||||
|
||||
if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX)
|
||||
if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) {
|
||||
emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
|
||||
}
|
||||
|
||||
if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
|
||||
emmc_dma) != EMMC_SUCCESS)
|
||||
emmc_dma) != EMMC_SUCCESS) {
|
||||
result = IO_FAIL;
|
||||
}
|
||||
|
||||
*length_read = length;
|
||||
fp->file_pos += (signed long long)length;
|
||||
|
|
@ -92,8 +95,8 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
|
|||
|
||||
if (emmcdrv_bootpartition == PARTITION_ID_USER) {
|
||||
emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en;
|
||||
if ((PARTITION_ID_BOOT_1 == emmcdrv_bootpartition) ||
|
||||
(PARTITION_ID_BOOT_2 == emmcdrv_bootpartition)) {
|
||||
if ((emmcdrv_bootpartition == PARTITION_ID_BOOT_1) ||
|
||||
(emmcdrv_bootpartition == PARTITION_ID_BOOT_2)) {
|
||||
current_file.partition = emmcdrv_bootpartition;
|
||||
|
||||
NOTICE("BL2: eMMC boot from partition %d\n",
|
||||
|
|
@ -103,16 +106,18 @@ static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
|
|||
return IO_FAIL;
|
||||
}
|
||||
|
||||
if ((PARTITION_ID_USER == block_spec->partition) ||
|
||||
(PARTITION_ID_BOOT_1 == block_spec->partition) ||
|
||||
(PARTITION_ID_BOOT_2 == block_spec->partition))
|
||||
if ((block_spec->partition == PARTITION_ID_USER) ||
|
||||
(block_spec->partition == PARTITION_ID_BOOT_1) ||
|
||||
(block_spec->partition == PARTITION_ID_BOOT_2)) {
|
||||
current_file.partition = block_spec->partition;
|
||||
else
|
||||
} else {
|
||||
current_file.partition = emmcdrv_bootpartition;
|
||||
}
|
||||
|
||||
done:
|
||||
if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS)
|
||||
if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) {
|
||||
return IO_FAIL;
|
||||
}
|
||||
|
||||
entity->info = (uintptr_t) ¤t_file;
|
||||
|
||||
|
|
@ -166,8 +171,9 @@ int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **dev_con)
|
|||
int32_t rc;
|
||||
|
||||
rc = io_register_device(&emmcdrv_dev_info);
|
||||
if (rc == IO_SUCCESS)
|
||||
if (rc == IO_SUCCESS) {
|
||||
*dev_con = &emmcdrv_dev_connector;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -11,8 +11,8 @@
|
|||
#include <drivers/io/io_storage.h>
|
||||
|
||||
#include "io_common.h"
|
||||
#include "io_private.h"
|
||||
#include "io_memdrv.h"
|
||||
#include "io_private.h"
|
||||
#include "rcar_def.h"
|
||||
|
||||
extern void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len);
|
||||
|
|
@ -21,7 +21,8 @@ static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
|
|||
io_dev_info_t **dev_info);
|
||||
static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
|
||||
|
||||
/* As we need to be able to keep state for seek, only one file can be open
|
||||
/*
|
||||
* As we need to be able to keep state for seek, only one file can be open
|
||||
* at a time. Make this a structure and point to the entity->info. When we
|
||||
* can malloc memory we can change this to support more open files.
|
||||
*/
|
||||
|
|
@ -43,12 +44,14 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
|
|||
{
|
||||
const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
|
||||
|
||||
/* Since we need to track open state for seek() we only allow one open
|
||||
/*
|
||||
* Since we need to track open state for seek() we only allow one open
|
||||
* spec at a time. When we have dynamic memory we can malloc and set
|
||||
* entity->info.
|
||||
*/
|
||||
if (current_file.in_use != 0U)
|
||||
if (current_file.in_use != 0U) {
|
||||
return IO_RESOURCES_EXHAUSTED;
|
||||
}
|
||||
|
||||
/* File cursor offset for seek and incremental reads etc. */
|
||||
current_file.base = block_spec->offset;
|
||||
|
|
@ -63,8 +66,9 @@ static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
|
|||
static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
|
||||
signed long long offset)
|
||||
{
|
||||
if (mode != IO_SEEK_SET)
|
||||
if (mode != IO_SEEK_SET) {
|
||||
return IO_FAIL;
|
||||
}
|
||||
|
||||
((file_state_t *) entity->info)->file_pos = offset;
|
||||
|
||||
|
|
@ -142,8 +146,9 @@ int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **dev_con)
|
|||
int32_t result;
|
||||
|
||||
result = io_register_device(&memdrv_dev_info);
|
||||
if (result == IO_SUCCESS)
|
||||
if (result == IO_SUCCESS) {
|
||||
*dev_con = &memdrv_dev_connector;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -8,8 +8,6 @@
|
|||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
|
|
@ -24,6 +22,7 @@
|
|||
#include "io_rcar.h"
|
||||
#include "io_common.h"
|
||||
#include "io_private.h"
|
||||
#include <platform_def.h>
|
||||
|
||||
extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
|
||||
uintptr_t *image_spec);
|
||||
|
|
@ -39,7 +38,8 @@ typedef struct {
|
|||
} plat_rcar_name_offset_t;
|
||||
|
||||
typedef struct {
|
||||
/* Put position above the struct to allow {0} on static init.
|
||||
/*
|
||||
* Put position above the struct to allow {0} on static init.
|
||||
* It is a workaround for a known bug in GCC
|
||||
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
|
||||
*/
|
||||
|
|
@ -136,9 +136,11 @@ int32_t rcar_get_certificate(const int32_t name, uint32_t *cert)
|
|||
{
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
int32_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
|
||||
if (name != cert_offset[i].name)
|
||||
if (name != cert_offset[i].name) {
|
||||
continue;
|
||||
}
|
||||
|
||||
*cert = RCAR_CERT_SIZE;
|
||||
*cert *= RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr);
|
||||
|
|
@ -157,12 +159,14 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
|
|||
int32_t i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(name_offset); i++) {
|
||||
if (name != name_offset[i].name)
|
||||
if (name != name_offset[i].name) {
|
||||
continue;
|
||||
}
|
||||
|
||||
addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr);
|
||||
if (rcar_image_number + 2 < addr)
|
||||
if (rcar_image_number + 2U < addr) {
|
||||
continue;
|
||||
}
|
||||
|
||||
*offset = rcar_image_header[addr];
|
||||
*cert = RCAR_CERT_SIZE;
|
||||
|
|
@ -175,8 +179,9 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
|
|||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
|
||||
if (name != cert_offset[i].name)
|
||||
if (name != cert_offset[i].name) {
|
||||
continue;
|
||||
}
|
||||
|
||||
*no_load = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr);
|
||||
*partition = 0U;
|
||||
|
|
@ -282,8 +287,9 @@ static int32_t check_load_area(uintptr_t dst, uintptr_t len)
|
|||
result = IO_FAIL;
|
||||
}
|
||||
done:
|
||||
if (result == IO_FAIL)
|
||||
if (result == IO_FAIL) {
|
||||
ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -307,14 +313,15 @@ static int32_t load_bl33x(void)
|
|||
BL338_IMAGE_ID
|
||||
};
|
||||
|
||||
if (loaded != IO_NOT_SUPPORTED)
|
||||
if (loaded != IO_NOT_SUPPORTED) {
|
||||
return loaded;
|
||||
}
|
||||
|
||||
for (i = 1; i < rcar_image_number; i++) {
|
||||
rc = file_to_offset(img[i], &offset, &cert, &noload,
|
||||
&partition);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("load_bl33x: failed to get offset\n");
|
||||
WARN("%s: failed to get offset\n", __func__);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
}
|
||||
|
|
@ -324,34 +331,34 @@ static int32_t load_bl33x(void)
|
|||
|
||||
rc = io_open(rcar_handle, rcar_spec, &handle);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("Failed to open FIP (%i)\n", rc);
|
||||
WARN("%s: Failed to open FIP (%i)\n", __func__, rc);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
}
|
||||
|
||||
rc = io_seek(handle, IO_SEEK_SET, offset);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("load_bl33x: failed to seek\n");
|
||||
WARN("%s: failed to seek\n", __func__);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
}
|
||||
|
||||
rc = check_load_area(dst, len);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("load_bl33x: check load area\n");
|
||||
WARN("%s: check load area\n", __func__);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
}
|
||||
|
||||
rc = io_read(handle, dst, len, &cnt);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("load_bl33x: failed to read\n");
|
||||
WARN("%s: failed to read\n", __func__);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
}
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
rc = auth_mod_verify_img(img[i], (void *)dst, len);
|
||||
if (rc) {
|
||||
if (rc != 0) {
|
||||
memset((void *)dst, 0x00, len);
|
||||
loaded = IO_FAIL;
|
||||
return loaded;
|
||||
|
|
@ -367,8 +374,7 @@ static int32_t load_bl33x(void)
|
|||
|
||||
static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
|
||||
{
|
||||
uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {
|
||||
0};
|
||||
uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
|
||||
uintptr_t handle;
|
||||
ssize_t offset;
|
||||
uint32_t i;
|
||||
|
|
@ -382,8 +388,9 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
|
|||
return IO_FAIL;
|
||||
}
|
||||
|
||||
if (RCAR_CERT_LOAD == rcar_cert_load)
|
||||
if (rcar_cert_load == RCAR_CERT_LOAD) {
|
||||
return IO_SUCCESS;
|
||||
}
|
||||
|
||||
rc = io_open(rcar_handle, rcar_spec, &handle);
|
||||
if (rc != IO_SUCCESS) {
|
||||
|
|
@ -391,16 +398,18 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
|
|||
return IO_FAIL;
|
||||
}
|
||||
|
||||
/* get start address list */
|
||||
/* [0] address num */
|
||||
/* [1] BL33-1 image address */
|
||||
/* [2] BL33-2 image address */
|
||||
/* [3] BL33-3 image address */
|
||||
/* [4] BL33-4 image address */
|
||||
/* [5] BL33-5 image address */
|
||||
/* [6] BL33-6 image address */
|
||||
/* [7] BL33-7 image address */
|
||||
/* [8] BL33-8 image address */
|
||||
/*
|
||||
* get start address list
|
||||
* [0] address num
|
||||
* [1] BL33-1 image address
|
||||
* [2] BL33-2 image address
|
||||
* [3] BL33-3 image address
|
||||
* [4] BL33-4 image address
|
||||
* [5] BL33-5 image address
|
||||
* [6] BL33-6 image address
|
||||
* [7] BL33-7 image address
|
||||
* [8] BL33-8 image address
|
||||
*/
|
||||
offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
|
||||
RCAR_FLASH_CERT_HEADER;
|
||||
rc = io_seek(handle, IO_SEEK_SET, offset);
|
||||
|
|
@ -447,8 +456,9 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
|
|||
rcar_cert_load = RCAR_CERT_LOAD;
|
||||
error:
|
||||
|
||||
if (rc != IO_SUCCESS)
|
||||
if (rc != IO_SUCCESS) {
|
||||
rc = IO_FAIL;
|
||||
}
|
||||
|
||||
io_close(handle);
|
||||
|
||||
|
|
@ -464,13 +474,15 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
|
|||
uint32_t noload, cert, len;
|
||||
int32_t rc;
|
||||
|
||||
/* Only one file open at a time. We need to track state (ie, file
|
||||
* cursor position). Since the header lives at * offset zero, this entry
|
||||
/*
|
||||
* Only one file open at a time. We need to track state (ie, file
|
||||
* cursor position). Since the header lives at offset zero, this entry
|
||||
* should never be zero in an active file.
|
||||
* Once the system supports dynamic memory allocation we will allow more
|
||||
* than one open file at a time. */
|
||||
* than one open file at a time.
|
||||
*/
|
||||
if (current_file.offset != 0U) {
|
||||
WARN("rcar_file_open : Only one open file at a time.\n");
|
||||
WARN("%s: Only one open file at a time.\n", __func__);
|
||||
return IO_RESOURCES_EXHAUSTED;
|
||||
}
|
||||
|
||||
|
|
@ -480,7 +492,7 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
|
|||
return IO_FAIL;
|
||||
}
|
||||
|
||||
if (noload) {
|
||||
if (noload != 0U) {
|
||||
current_file.offset = 1;
|
||||
current_file.dst = 0;
|
||||
current_file.size = 1;
|
||||
|
|
@ -494,12 +506,10 @@ static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
|
|||
|
||||
rcar_read_certificate((uint64_t) cert, &len, &dst);
|
||||
|
||||
/*----------------*
|
||||
* Baylibre: HACK *
|
||||
*----------------*/
|
||||
if (BL31_IMAGE_ID == spec->offset && len < RCAR_TRUSTED_SRAM_SIZE) {
|
||||
WARN("r-car ignoring the BL31 size from certificate,"
|
||||
"using RCAR_TRUSTED_SRAM_SIZE instead\n");
|
||||
/* Baylibre: HACK */
|
||||
if (spec->offset == BL31_IMAGE_ID && len < RCAR_TRUSTED_SRAM_SIZE) {
|
||||
WARN("%s,%s\n", "r-car ignoring the BL31 size from certificate",
|
||||
"using RCAR_TRUSTED_SRAM_SIZE instead");
|
||||
len = RCAR_TRUSTED_SRAM_SIZE;
|
||||
}
|
||||
|
||||
|
|
@ -536,7 +546,7 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
|
|||
#else
|
||||
static uint32_t load_bl33x_counter;
|
||||
#endif
|
||||
if (current_file.no_load) {
|
||||
if (current_file.no_load != 0U) {
|
||||
*cnt = length;
|
||||
return IO_SUCCESS;
|
||||
}
|
||||
|
|
@ -551,14 +561,14 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
|
|||
|
||||
rc = io_seek(handle, IO_SEEK_SET, offset);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("rcar_file_read: failed to seek\n");
|
||||
WARN("%s: failed to seek\n", __func__);
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33) {
|
||||
rc = check_load_area(buffer, length);
|
||||
if (rc != IO_SUCCESS) {
|
||||
WARN("rcar_file_read: load area err\n");
|
||||
WARN("%s: load area err\n", __func__);
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
|
@ -573,8 +583,9 @@ static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
|
|||
io_close(handle);
|
||||
|
||||
load_bl33x_counter += 1;
|
||||
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X)
|
||||
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X) {
|
||||
return load_bl33x();
|
||||
}
|
||||
|
||||
return IO_SUCCESS;
|
||||
error:
|
||||
|
|
@ -584,8 +595,9 @@ error:
|
|||
|
||||
static int32_t rcar_file_close(io_entity_t *entity)
|
||||
{
|
||||
if (current_file.offset)
|
||||
if (current_file.offset != 0U) {
|
||||
memset(¤t_file, 0, sizeof(current_file));
|
||||
}
|
||||
|
||||
entity->info = 0U;
|
||||
|
||||
|
|
@ -634,8 +646,9 @@ int32_t rcar_register_io_dev(const io_dev_connector_t **dev_con)
|
|||
int32_t result;
|
||||
|
||||
result = io_register_device(&rcar_dev_info);
|
||||
if (result == IO_SUCCESS)
|
||||
if (result == IO_SUCCESS) {
|
||||
*dev_con = &rcar_dev_connector;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -16,10 +16,10 @@
|
|||
#include <plat/common/platform.h>
|
||||
|
||||
#include "iic_dvfs.h"
|
||||
#include "rcar_def.h"
|
||||
#include "rcar_private.h"
|
||||
#include "micro_delay.h"
|
||||
#include "pwrc.h"
|
||||
#include "rcar_def.h"
|
||||
#include "rcar_private.h"
|
||||
|
||||
/*
|
||||
* Someday there will be a generic power controller api. At the moment each
|
||||
|
|
@ -140,7 +140,7 @@ RCAR_INSTANTIATE_LOCK
|
|||
#define PMIC_BKUP_MODE_CNT (0x20U)
|
||||
#define PMIC_QLLM_CNT (0x27U)
|
||||
#define PMIC_RETRY_MAX (100U)
|
||||
#endif
|
||||
#endif /* PMIC_ROHM_BD9571 */
|
||||
#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
|
||||
#define RCAR_CA53CPU_NUM_MAX (4U)
|
||||
#define RCAR_CA57CPU_NUM_MAX (4U)
|
||||
|
|
@ -320,11 +320,13 @@ void rcar_pwrc_clusteroff(uint64_t mpidr)
|
|||
c = rcar_pwrc_get_mpidr_cluster(mpidr);
|
||||
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
|
||||
|
||||
if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
|
||||
if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
|
||||
if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
/* all of the CPUs in the cluster is in the CoreStandby mode */
|
||||
mmio_write_32(dst, MODE_L2_DOWN);
|
||||
|
|
@ -343,7 +345,7 @@ static void rcar_pwrc_save_timer_state(void)
|
|||
rcar_pwrc_saved_cntfid =
|
||||
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
|
||||
}
|
||||
#endif
|
||||
#endif /* RCAR_SYSTEM_SUSPEND */
|
||||
|
||||
void rcar_pwrc_restore_timer_state(void)
|
||||
{
|
||||
|
|
@ -427,11 +429,13 @@ static void __attribute__ ((section(".system_ram")))
|
|||
product = reg & PRR_PRODUCT_MASK;
|
||||
cut = reg & PRR_CUT_MASK;
|
||||
|
||||
if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
|
||||
if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
|
||||
goto self_refresh;
|
||||
}
|
||||
|
||||
if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
|
||||
if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
|
||||
goto self_refresh;
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
|
||||
|
||||
|
|
@ -533,8 +537,10 @@ static void __attribute__ ((section(".system_ram")))
|
|||
while (mmio_read_32(DBSC4_REG_DBWAIT))
|
||||
;
|
||||
|
||||
/* Set the auto-refresh enable register */
|
||||
/* Set the ARFEN bit to 0 in the DBRFEN */
|
||||
/*
|
||||
* Set the auto-refresh enable register
|
||||
* Set the ARFEN bit to 0 in the DBRFEN
|
||||
*/
|
||||
mmio_write_32(DBSC4_REG_DBRFEN, 0);
|
||||
|
||||
mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
|
||||
|
|
@ -835,7 +841,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
|
|||
uint64_t my_cpu;
|
||||
int32_t rtn;
|
||||
uint32_t my_cluster_type;
|
||||
|
||||
const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
|
||||
RCAR_CLUSTER_CA53,
|
||||
RCAR_CLUSTER_CA57
|
||||
|
|
@ -861,6 +866,6 @@ int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
|
|||
}
|
||||
}
|
||||
}
|
||||
return (rtn);
|
||||
|
||||
return rtn;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -123,7 +123,8 @@
|
|||
.globl console_rcar_putc
|
||||
.globl console_rcar_flush
|
||||
|
||||
/* -----------------------------------------------
|
||||
/*
|
||||
* -----------------------------------------------
|
||||
* int console_rcar_register(
|
||||
* uintptr_t base, uint32_t clk, uint32_t baud,
|
||||
* console_t *console)
|
||||
|
|
@ -154,7 +155,7 @@ register_fail:
|
|||
ret x7
|
||||
endfunc console_rcar_register
|
||||
|
||||
/* -----------------------------------------------
|
||||
/*
|
||||
* int console_rcar_init(unsigned long base_addr,
|
||||
* unsigned int uart_clk, unsigned int baud_rate)
|
||||
* Function to initialize the console without a
|
||||
|
|
@ -166,7 +167,6 @@ endfunc console_rcar_register
|
|||
* w2 - Baud rate
|
||||
* Out: return 1 on success
|
||||
* Clobber list : x1, x2
|
||||
* -----------------------------------------------
|
||||
*/
|
||||
func console_rcar_init
|
||||
ldr x0, =CPG_BASE
|
||||
|
|
@ -188,8 +188,10 @@ func console_rcar_init
|
|||
ldrh w1, [x0, #SCIF_SCFCR]
|
||||
orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
|
||||
strh w1, [x0, #SCIF_SCFCR]
|
||||
/* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
|
||||
in SCLSR, then clear them to 0 */
|
||||
/*
|
||||
* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
|
||||
* in SCLSR, then clear them to 0
|
||||
*/
|
||||
mov w1, #SCFSR_INIT_DATA
|
||||
strh w1, [x0, #SCIF_SCFSR]
|
||||
mov w1, #0
|
||||
|
|
@ -265,7 +267,7 @@ func console_rcar_init
|
|||
ret
|
||||
endfunc console_rcar_init
|
||||
|
||||
/* --------------------------------------------------------
|
||||
/*
|
||||
* int console_rcar_putc(int c, unsigned int base_addr)
|
||||
* Function to output a character over the console. It
|
||||
* returns the character printed on success or -1 on error.
|
||||
|
|
@ -273,7 +275,6 @@ endfunc console_rcar_init
|
|||
* x1 - pointer to console_t structure
|
||||
* Out : return -1 on error else return character.
|
||||
* Clobber list : x2
|
||||
* --------------------------------------------------------
|
||||
*/
|
||||
func console_rcar_putc
|
||||
ldr x1, =SCIF_BASE
|
||||
|
|
@ -304,12 +305,11 @@ func console_rcar_putc
|
|||
ret
|
||||
endfunc console_rcar_putc
|
||||
|
||||
/* ---------------------------------------------
|
||||
/*
|
||||
* void console_rcar_flush(void)
|
||||
* Function to force a write of all buffered
|
||||
* data that hasn't been output. It returns void
|
||||
* Clobber list : x0, x1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func console_rcar_flush
|
||||
ldr x0, =SCIF_BASE
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -162,6 +162,6 @@ void rcar_swdt_exec(uint64_t p)
|
|||
gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
|
||||
rcar_swdt_release();
|
||||
ERROR("\n");
|
||||
ERROR("System WDT overflow, occured address is %p\n", (void *)p);
|
||||
ERROR("System WDT overflow, occurred address is %p\n", (void *)p);
|
||||
panic();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue