From e8b7a80436c2bc81c61fc4703d6580f2fe9226a9 Mon Sep 17 00:00:00 2001
From: Anurag Koul <anurag.koul@arm.com>
Date: Wed, 25 Aug 2021 19:34:20 +0530
Subject: [PATCH] fix(morello): fix SoC reference clock frequency

Morello Specification specifies the system
reference clock frequency as 50MHz so the frequency
has been changed from 100MHz to 50MHz.

Change-Id: I25577b04aa54ed82b7e9df69ac8e40ac54a9b111
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
---
 fdts/morello.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index 52c04cd96..eb2202a04 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -58,7 +58,7 @@
 				  "mhu_hpri_rx";
 		#mbox-cells = <2>;
 		mbox-name = "ARM-MHU";
-		clocks = <&soc_refclk100mhz>;
+		clocks = <&soc_refclk50mhz>;
 		clock-names = "apb_pclk";
 	};
 
@@ -81,10 +81,10 @@
 		};
 	};
 
-	soc_refclk100mhz: refclk100mhz {
+	soc_refclk50mhz: refclk50mhz {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <100000000>;
+		clock-frequency = <50000000>;
 		clock-output-names = "apb_pclk";
 	};
 
@@ -99,7 +99,7 @@
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x0 0x2a400000 0x0 0x1000>;
 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+		clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
 		clock-names = "uartclk", "apb_pclk";
 		status = "okay";
 	};