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Merge pull request #1560 from vwadekar/denver-fixes-918 

Recent Denver CPU fixes from downstream
This commit is contained in:
Dimitris Papastamos 2018-09-05 12:18:37 +01:00 committed by GitHub
parent 8e7940d15b 6cf8d65f27
commit e8e0717297
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 60 additions and 5 deletions
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16
include/lib/cpus/aarch64/denver.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,6 +20,20 @@
/* CPU state ids - implementation defined */
#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
/* Speculative store buffering */
#define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11)
#define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18)
/* Speculative memory disambiguation */
#define DENVER_CPU_DIS_MD_EL3 (U(1) << 9)
#define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17)
/* Core power management states */
#define DENVER_CPU_PMSTATE_C1 U(0x1)
#define DENVER_CPU_PMSTATE_C6 U(0x6)
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
#ifndef __ASSEMBLY__
/* Disable Dynamic Code Optimisation */

49
lib/cpus/aarch64/denver.S
View File

@ -156,11 +156,12 @@ endfunc denver_disable_ext_debug
* ----------------------------------------------------
*/
func denver_enable_dco
mrs x0, mpidr_el1
and x0, x0, #0xF
mov x3, x30
bl plat_my_core_pos
mov x1, #1
lsl x1, x1, x0
msr s3_0_c15_c0_2, x1
mov x30, x3
ret
endfunc denver_enable_dco
@ -170,9 +171,10 @@ endfunc denver_enable_dco
*/
func denver_disable_dco
mov x3, x30
/* turn off background work */
mrs x0, mpidr_el1
and x0, x0, #0xF
bl plat_my_core_pos
mov x1, #1
lsl x1, x1, x0
lsl x2, x1, #16
@ -186,6 +188,7 @@ func denver_disable_dco
and x2, x2, x1
cbnz x2, 1b
mov x30, x3
ret
endfunc denver_disable_dco
@ -208,6 +211,15 @@ func check_errata_cve_2017_5715
ret
endfunc check_errata_cve_2017_5715
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
/* -------------------------------------------------
* The CPU Ops reset function for Denver.
* -------------------------------------------------
@ -233,6 +245,34 @@ func denver_reset_func
msr vbar_el3, x0
#endif
#if WORKAROUND_CVE_2018_3639
/*
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
* bits in the ACTLR_EL3 register to disable speculative
* store buffer and memory disambiguation.
*/
mrs x0, midr_el1
mov_imm x1, DENVER_MIDR_PN4
cmp x0, x1
mrs x0, actlr_el3
mov x1, #(DENVER_CPU_DIS_MD_EL3 | DENVER_CPU_DIS_SSB_EL3)
mov x2, #(DENVER_PN4_CPU_DIS_MD_EL3 | DENVER_PN4_CPU_DIS_SSB_EL3)
csel x3, x1, x2, ne
orr x0, x0, x3
msr actlr_el3, x0
isb
dsb sy
#endif
/* ----------------------------------------------------
* Reset ACTLR.PMSTATE to C1 state
* ----------------------------------------------------
*/
mrs x0, actlr_el1
bic x0, x0, #DENVER_CPU_PMSTATE_MASK
orr x0, x0, #DENVER_CPU_PMSTATE_C1
msr actlr_el1, x0
/* ----------------------------------------------------
* Enable dynamic code optimizer (DCO)
* ----------------------------------------------------
@ -282,6 +322,7 @@ func denver_errata_report
* checking functions of each errata.
*/
report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
ldp x8, x30, [sp], #16
ret