From e92655849d0a9e5893eb2d7e5f42cf8b931d4db6 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 25 May 2022 12:45:22 +0100 Subject: [PATCH] fix(include/aarch64): fix encodings for MPAMVPM* registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes the following encodings in the System register encoding space for the MPAM registers. The encodings now match with the Arm® Architecture Reference Manual Supplement for MPAM. * MPAMVPM0_EL2 * MPAMVPM1_EL2 * MPAMVPM2_EL2 * MPAMVPM3_EL2 * MPAMVPM4_EL2 * MPAMVPM5_EL2 * MPAMVPM6_EL2 * MPAMVPM7_EL2 * MPAMVPMV_EL2 Signed-off-by: Varun Wadekar Change-Id: Ib339412de6a9c945a3307f3f347fe7b2efabdc18 --- include/arch/aarch64/arch.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index dfb9fe4b8..e55d33fd3 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -108,14 +108,14 @@ #define HFGWTR_EL2 S3_4_C1_C1_5 #define ICH_HCR_EL2 S3_4_C12_C11_0 #define ICH_VMCR_EL2 S3_4_C12_C11_7 -#define MPAMVPM0_EL2 S3_4_C10_C5_0 -#define MPAMVPM1_EL2 S3_4_C10_C5_1 -#define MPAMVPM2_EL2 S3_4_C10_C5_2 -#define MPAMVPM3_EL2 S3_4_C10_C5_3 -#define MPAMVPM4_EL2 S3_4_C10_C5_4 -#define MPAMVPM5_EL2 S3_4_C10_C5_5 -#define MPAMVPM6_EL2 S3_4_C10_C5_6 -#define MPAMVPM7_EL2 S3_4_C10_C5_7 +#define MPAMVPM0_EL2 S3_4_C10_C6_0 +#define MPAMVPM1_EL2 S3_4_C10_C6_1 +#define MPAMVPM2_EL2 S3_4_C10_C6_2 +#define MPAMVPM3_EL2 S3_4_C10_C6_3 +#define MPAMVPM4_EL2 S3_4_C10_C6_4 +#define MPAMVPM5_EL2 S3_4_C10_C6_5 +#define MPAMVPM6_EL2 S3_4_C10_C6_6 +#define MPAMVPM7_EL2 S3_4_C10_C6_7 #define MPAMVPMV_EL2 S3_4_C10_C4_1 #define TRFCR_EL2 S3_4_C1_C2_1 #define PMSCR_EL2 S3_4_C9_C9_0