Tegra: support for silicon/simulation platforms
This patch adds support to identify the underlying platform on which we are running. The currently supported platforms are actual silicon and simulation platforms. Change-Id: Iadf96e79ec663b3dbd1a18e9bb95ffcdb82fc8af Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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#
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# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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@ -57,6 +57,7 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_fiq_glue.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_platform.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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${COMMON_DIR}/tegra_topology.c
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@ -0,0 +1,167 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <mmio.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/*******************************************************************************
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* Tegra platforms
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******************************************************************************/
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typedef enum tegra_platform {
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TEGRA_PLATFORM_SILICON = 0,
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TEGRA_PLATFORM_QT,
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TEGRA_PLATFORM_FPGA,
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TEGRA_PLATFORM_EMULATION,
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TEGRA_PLATFORM_MAX,
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} tegra_platform_t;
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/*******************************************************************************
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* Tegra macros defining all the SoC minor versions
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******************************************************************************/
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#define TEGRA_MINOR_QT 0
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#define TEGRA_MINOR_FPGA 1
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#define TEGRA_MINOR_EMULATION_MIN 2
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#define TEGRA_MINOR_EMULATION_MAX 10
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/*******************************************************************************
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* Tegra major, minor version helper macros
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******************************************************************************/
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#define MAJOR_VERSION_SHIFT 0x4
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#define MAJOR_VERSION_MASK 0xF
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#define MINOR_VERSION_SHIFT 0x10
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#define MINOR_VERSION_MASK 0xF
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#define CHIP_ID_SHIFT 8
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#define CHIP_ID_MASK 0xFF
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/*******************************************************************************
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* Tegra chip ID values
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******************************************************************************/
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typedef enum tegra_chipid {
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TEGRA_CHIPID_TEGRA13 = 0x13,
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TEGRA_CHIPID_TEGRA21 = 0x21,
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} tegra_chipid_t;
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/*
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* Read the chip ID value
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*/
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static uint32_t tegra_get_chipid(void)
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{
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return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET);
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}
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/*
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* Read the chip's major version from chip ID value
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*/
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static uint32_t tegra_get_chipid_major(void)
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{
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return (tegra_get_chipid() >> MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
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}
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/*
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* Read the chip's minor version from the chip ID value
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*/
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static uint32_t tegra_get_chipid_minor(void)
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{
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return (tegra_get_chipid() >> MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
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}
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uint8_t tegra_chipid_is_t132(void)
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{
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uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
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return (chip_id == TEGRA_CHIPID_TEGRA13);
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}
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uint8_t tegra_chipid_is_t210(void)
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{
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uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
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return (chip_id == TEGRA_CHIPID_TEGRA21);
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}
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/*
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* Read the chip ID value and derive the platform
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*/
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static tegra_platform_t tegra_get_platform(void)
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{
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uint32_t major = tegra_get_chipid_major();
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uint32_t minor = tegra_get_chipid_minor();
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/* Actual silicon platforms have a non-zero major version */
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if (major > 0)
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return TEGRA_PLATFORM_SILICON;
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/*
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* The minor version number is used by simulation platforms
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*/
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/*
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* Cadence's QuickTurn emulation system is a Solaris-based
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* chip emulation system
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*/
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if (minor == TEGRA_MINOR_QT)
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return TEGRA_PLATFORM_QT;
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/*
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* FPGAs are used during early software/hardware development
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*/
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if (minor == TEGRA_MINOR_FPGA)
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return TEGRA_PLATFORM_FPGA;
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/* Minor version reserved for other emulation platforms */
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if ((minor > TEGRA_MINOR_FPGA) && (minor <= TEGRA_MINOR_EMULATION_MAX))
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return TEGRA_PLATFORM_EMULATION;
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/* unsupported platform */
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return TEGRA_PLATFORM_MAX;
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}
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uint8_t tegra_platform_is_silicon(void)
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{
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return (tegra_get_platform() == TEGRA_PLATFORM_SILICON);
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}
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uint8_t tegra_platform_is_qt(void)
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{
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return (tegra_get_platform() == TEGRA_PLATFORM_QT);
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}
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uint8_t tegra_platform_is_fpga(void)
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{
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return (tegra_get_platform() == TEGRA_PLATFORM_FPGA);
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}
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uint8_t tegra_platform_is_emulation(void)
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{
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return (tegra_get_platform() == TEGRA_PLATFORM_EMULATION);
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}
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@ -79,6 +79,12 @@
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******************************************************************************/
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#define TEGRA_EVP_BASE 0x6000F000
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/*******************************************************************************
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* Tegra Miscellaneous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE 0x70000000
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#define HARDWARE_REVISION_OFFSET 0x804
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/*******************************************************************************
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* Tegra UART controller base addresses
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_EVP_BASE 0x6000F000
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/*******************************************************************************
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* Tegra Miscellaneous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE 0x70000000
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#define HARDWARE_REVISION_OFFSET 0x804
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/*******************************************************************************
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* Tegra UART controller base addresses
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******************************************************************************/
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@ -0,0 +1,50 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TEGRA_PLATFORM_H__
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#define __TEGRA_PLATFORM_H__
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#include <sys/cdefs.h>
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/*
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* Tegra chip identifiers
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*/
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uint8_t tegra_is_t132(void);
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uint8_t tegra_is_t210(void);
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/*
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* Tegra platform identifiers
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*/
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uint8_t tegra_platform_is_silicon(void);
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uint8_t tegra_platform_is_qt(void);
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uint8_t tegra_platform_is_emulation(void);
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uint8_t tegra_platform_is_fpga(void);
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#endif /* __TEGRA_PLATFORM_H__ */
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