From 63446c27d11453faacfddecffa44d3880615d412 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 8 Mar 2022 10:37:43 -0600 Subject: [PATCH] fix(errata): workaround for Cortex-X2 erratum 2147715 Cortex-X2 erratum 2147715 is a Cat B erratum that applies to revision r2p0 and is fixed in r2p1. The workaround is to set CPUACTLR_EL1[22]=1, which will cause the CFP instruction to invalidate all branch predictor resources regardless of context. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100/latest Signed-off-by: Bipin Ravi Change-Id: I2d81867486d9130f2c36cd4554ca9a8f37254b57 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_x2.h | 6 ++++ lib/cpus/aarch64/cortex_x2.S | 40 +++++++++++++++++++++-- lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 56 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index af0e76993..3029458ef 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -490,6 +490,10 @@ For Cortex-X2, the following errata build flags are defined : Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU, it is fixed in r2p1. +- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to + Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU, + it is fixed in r2p1. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 62530e219..92140b1e2 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -33,6 +33,12 @@ #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control Register definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) + /******************************************************************************* * CPU Auxiliary Control Register 5 definitions ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 9586a5b34..90a906b25 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -237,6 +237,36 @@ func check_errata_cve_2022_23960 ret endfunc check_errata_cve_2022_23960 + /* --------------------------------------------------------- + * Errata Workaround for Cortex-X2 Errata 2147715. + * This applies only to revisions r2p0 and is fixed in r2p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * --------------------------------------------------------- + */ +func errata_x2_2147715_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_2147715 + cbz x0, 1f + + /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ + mrs x1, CORTEX_X2_CPUACTLR_EL1 + orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22 + msr CORTEX_X2_CPUACTLR_EL1, x1 + +1: + ret x17 +endfunc errata_x2_2147715_wa + +func check_errata_2147715 + /* Applies to r2p0 */ + mov x1, #0x20 + mov x2, #0x20 + b cpu_rev_var_range +endfunc check_errata_2147715 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -268,10 +298,11 @@ func cortex_x2_errata_report * checking functions of each errata. */ report_errata ERRATA_X2_2002765, cortex_x2, 2002765 - report_errata ERRATA_X2_2058056, cortex_x2, 2058056 - report_errata ERRATA_X2_2083908, cortex_x2, 2083908 report_errata ERRATA_X2_2017096, cortex_x2, 2017096 + report_errata ERRATA_X2_2058056, cortex_x2, 2058056 report_errata ERRATA_X2_2081180, cortex_x2, 2081180 + report_errata ERRATA_X2_2083908, cortex_x2, 2083908 + report_errata ERRATA_X2_2147715, cortex_x2, 2147715 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 @@ -321,6 +352,11 @@ func cortex_x2_reset_func bl errata_x2_2216384_wa #endif +#if ERRATA_X2_2147715 + mov x0, x18 + bl errata_x2_2147715_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-X2 generic vectors are overridden to apply errata diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 8840f8ed5..462ca9dff 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -547,6 +547,10 @@ ERRATA_X2_2081180 ?=0 # r2p1. ERRATA_X2_2216384 ?=0 +# Flag to apply erratum 2147715 workaround during reset. This erratum applies +# only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1. +ERRATA_X2_2147715 ?=0 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. ERRATA_A510_1922240 ?=0 @@ -1046,6 +1050,10 @@ $(eval $(call add_define,ERRATA_X2_2081180)) $(eval $(call assert_boolean,ERRATA_X2_2216384)) $(eval $(call add_define,ERRATA_X2_2216384)) +# Process ERRATA_X2_2147715 flag +$(eval $(call assert_boolean,ERRATA_X2_2147715)) +$(eval $(call add_define,ERRATA_X2_2147715)) + # Process ERRATA_A510_1922240 flag $(eval $(call assert_boolean,ERRATA_A510_1922240)) $(eval $(call add_define,ERRATA_A510_1922240))