rcar_gen3: drivers: pfc: D3: Drop unused M3W check
Drop check for SoC being M3W ES1.0 , this check is clearly bogus, as this code can never be executed on M3W ES 1.0. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If6087f1c217393dc65d20f6591eca40188563710
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -792,13 +792,6 @@
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#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
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#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
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/* SCIF3 Registers for Dummy write */
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#define SCIF3_BASE (0xE6C50000U)
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#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U)
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#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU)
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#define SCFCR_DATA (0x0000U)
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/* Realtime module stop control */
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#define CPG_BASE (0xE6150000U)
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#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
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@ -832,27 +825,12 @@
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#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */
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#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */
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static void pfc_reg_write(uint32_t addr, uint32_t data);
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static void pfc_reg_write(uint32_t addr, uint32_t data)
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{
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uint32_t prr;
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prr = mmio_read_32(RCAR_PRR);
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prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
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mmio_write_32(PFC_PMMR, ~data);
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if (prr == (RCAR_PRODUCT_M3_CUT10)) {
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mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
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}
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mmio_write_32((uintptr_t)addr, data);
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if (prr == (RCAR_PRODUCT_M3_CUT10)) {
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mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
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}
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}
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void pfc_init_d3(void)
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{
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/* initialize module select */
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