Tegra: memmap Tegra micro-seconds timer controller
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -354,6 +354,12 @@ void bl31_plat_arch_setup(void)
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MT_DEVICE | MT_RW | MT_SECURE);
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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#endif
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/* map on-chip free running uS timer */
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mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
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page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
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(uint64_t)TEGRA_TMRUS_SIZE,
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MT_DEVICE | MT_RO | MT_SECURE);
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/* add MMIO space */
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map)
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if (plat_mmio_map)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -58,6 +58,7 @@
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* Tegra micro-seconds timer constants
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* Tegra micro-seconds timer constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_SIZE 0x1000
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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* Tegra Clock and Reset Controller constants
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@ -237,6 +237,7 @@
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* Tegra micro-seconds timer constants
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* Tegra micro-seconds timer constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x0C2E0000
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#define TEGRA_TMRUS_BASE 0x0C2E0000
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#define TEGRA_TMRUS_SIZE 0x1000
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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* Tegra Power Mgmt Controller constants
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -83,6 +83,7 @@
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* Tegra micro-seconds timer constants
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* Tegra micro-seconds timer constants
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_SIZE 0x1000
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/*******************************************************************************
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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* Tegra Clock and Reset Controller constants
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@ -40,7 +40,7 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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PLATFORM_MAX_CPUS_PER_CLUSTER := 4
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
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MAX_XLAT_TABLES := 3
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MAX_XLAT_TABLES := 4
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$(eval $(call add_define,MAX_XLAT_TABLES))
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$(eval $(call add_define,MAX_XLAT_TABLES))
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MAX_MMAP_REGIONS := 8
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MAX_MMAP_REGIONS := 8
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