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intel: Refactor common platform code [2/5] 

Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
This commit is contained in:
Hadi Asyrafi 2019-10-23 17:02:55 +08:00
parent 328718f254
commit e9b5e360de
11 changed files with 39 additions and 277 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
plat/intel/soc/agilex/bl2_plat_setup.c
View File

@ -15,19 +15,18 @@
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <platform_def.h>
#include <socfpga_private.h>
#include "agilex_clock_manager.h"
#include "agilex_mailbox.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
#include "agilex_private.h"
#include "agilex_reset_manager.h"
#include "agilex_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "socfpga_private.h"
#include "wdt/watchdog.h"

34
plat/intel/soc/agilex/include/agilex_private.h
View File

@ -1,34 +0,0 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef AGX_PRIVATE_H
#define AGX_PRIVATE_H
#define AGX_MMC_REG_BASE 0xff808000
#define EMMC_DESC_SIZE (1<<20)
#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
.clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \
.reg_base = AGX_MMC_REG_BASE \
}
typedef enum {
BOOT_SOURCE_FPGA = 0,
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
BOOT_SOURCE_QSPI
} boot_source_type;
void enable_nonsecure_access(void);
void socfpga_io_setup(int boot_source);
#endif

2
plat/intel/soc/agilex/platform.mk
View File

@ -37,7 +37,7 @@ BL2_SOURCES += \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/agilex/bl2_plat_setup.c \
plat/intel/soc/agilex/socfpga_storage.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \

3
plat/intel/soc/common/aarch64/platform_common.c
View File

@ -8,7 +8,8 @@
#include <arch_helpers.h>
#include <platform_def.h>
#include <plat/common/platform.h>
#include <socfpga_private.h>
#include "socfpga_private.h"
unsigned int plat_get_syscnt_freq2(void)

32
plat/intel/soc/common/include/socfpga_private.h
View File

@ -4,12 +4,38 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_PRIVATE_H
#define PLATFORM_PRIVATE_H
#ifndef SOCFPGA_PRIVATE_H
#define SOCFPGA_PRIVATE_H
#include "socfpga_plat_def.h"
#define EMMC_DESC_SIZE (1<<20)
#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
.clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \
.reg_base = SOCFPGA_MMC_REG_BASE \
}
typedef enum {
BOOT_SOURCE_FPGA = 0,
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
BOOT_SOURCE_QSPI
} boot_source_type;
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void enable_nonsecure_access(void);
void socfpga_io_setup(int boot_source);
void socfgpa_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long ro_start,
@ -36,4 +62,4 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void);
unsigned long socfpga_get_ns_image_entrypoint(void);
#endif /* PLATFORM_PRIVATE_H */
#endif /* SOCFPGA_PRIVATE_H */

2
plat/intel/soc/agilex/socfpga_storage.c → plat/intel/soc/common/socfpga_storage.c
View File

@ -19,7 +19,7 @@
#include <lib/mmio.h>
#include <tools_share/firmware_image_package.h>
#include "agilex_private.h"
#include "socfpga_private.h"
#define PLAT_FIP_BASE (0)
#define PLAT_FIP_MAX_SIZE (0x1000000)

7
plat/intel/soc/stratix10/bl2_plat_setup.c
View File

@ -19,7 +19,6 @@
#include <common/image_decompress.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <socfpga_private.h>
#include <drivers/synopsys/dw_mmc.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
@ -28,10 +27,10 @@
#include "s10_reset_manager.h"
#include "s10_clock_manager.h"
#include "s10_pinmux.h"
#include "stratix10_private.h"
#include "include/s10_mailbox.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "socfpga_private.h"
#include "wdt/watchdog.h"
@ -115,7 +114,7 @@ void bl2_el3_plat_arch_setup(void)
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
dw_mmc_init(&params, &info);
stratix10_io_setup(boot_source);
socfpga_io_setup(boot_source);
break;
case BOOT_SOURCE_QSPI:
@ -124,7 +123,7 @@ void bl2_el3_plat_arch_setup(void)
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
stratix10_io_setup(boot_source);
socfpga_io_setup(boot_source);
break;
default:

2
plat/intel/soc/stratix10/bl31_plat_setup.c
View File

@ -22,7 +22,7 @@
#include <plat/common/platform.h>
#include <platform_def.h>
#include "stratix10_private.h"
#include "socfpga_private.h"
#include "s10_reset_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"

34
plat/intel/soc/stratix10/include/stratix10_private.h
View File

@ -1,34 +0,0 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __S10_PRIVATE_H__
#define __S10_PRIVATE_H__
#define S10_MMC_REG_BASE 0xff808000
#define EMMC_DESC_SIZE (1<<20)
#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
.clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \
.reg_base = S10_MMC_REG_BASE, \
\
}
typedef enum {
BOOT_SOURCE_FPGA = 0,
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
BOOT_SOURCE_QSPI,
} boot_source_type;
void enable_nonsecure_access(void);
void stratix10_io_setup(int boot_source);
#endif

195
plat/intel/soc/stratix10/plat_storage.c
View File

@ -1,195 +0,0 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <common/debug.h>
#include <drivers/mmc.h>
#include <tools_share/firmware_image_package.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
#include <drivers/io/io_storage.h>
#include <lib/mmio.h>
#include <drivers/partition/partition.h>
#include <lib/semihosting.h>
#include <string.h>
#include <lib/utils.h>
#include <common/tbbr/tbbr_img_def.h>
#include "platform_def.h"
#include "stratix10_private.h"
#define STRATIX10_FIP_BASE (0)
#define STRATIX10_FIP_MAX_SIZE (0x1000000)
#define STRATIX10_MMC_DATA_BASE (0xffe3c000)
#define STRATIX10_MMC_DATA_SIZE (0x2000)
#define STRATIX10_QSPI_DATA_BASE (0x3C00000)
#define STRATIX10_QSPI_DATA_SIZE (0x1000000)
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;
static uintptr_t fip_dev_handle;
static uintptr_t boot_dev_handle;
static const io_uuid_spec_t bl2_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
};
static const io_uuid_spec_t bl31_uuid_spec = {
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
};
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
uintptr_t a2_lba_offset;
const char a2[] = {0xa2, 0x0};
static const io_block_spec_t gpt_block_spec = {
.offset = 0,
.length = MMC_BLOCK_SIZE
};
static int check_fip(const uintptr_t spec);
static int check_dev(const uintptr_t spec);
static io_block_dev_spec_t boot_dev_spec;
static int (*register_io_dev)(const io_dev_connector_t **);
static io_block_spec_t fip_spec = {
.offset = STRATIX10_FIP_BASE,
.length = STRATIX10_FIP_MAX_SIZE,
};
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
[FIP_IMAGE_ID] = {
&boot_dev_handle,
(uintptr_t)&fip_spec,
check_dev
},
[BL2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl2_uuid_spec,
check_fip
},
[BL31_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl31_uuid_spec,
check_fip
},
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t) &bl33_uuid_spec,
check_fip
},
[GPT_IMAGE_ID] = {
&boot_dev_handle,
(uintptr_t) &gpt_block_spec,
check_dev
},
};
static int check_dev(const uintptr_t spec)
{
int result;
uintptr_t local_handle;
result = io_dev_init(boot_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(boot_dev_handle, spec, &local_handle);
if (result == 0)
io_close(local_handle);
}
return result;
}
static int check_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
if (result == 0) {
result = io_open(fip_dev_handle, spec, &local_image_handle);
if (result == 0)
io_close(local_image_handle);
}
return result;
}
void stratix10_io_setup(int boot_source)
{
int result;
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
register_io_dev = &register_io_dev_block;
boot_dev_spec.buffer.offset = STRATIX10_MMC_DATA_BASE;
boot_dev_spec.buffer.length = MMC_BLOCK_SIZE;
boot_dev_spec.ops.read = mmc_read_blocks;
boot_dev_spec.ops.write = mmc_write_blocks;
boot_dev_spec.block_size = MMC_BLOCK_SIZE;
break;
case BOOT_SOURCE_QSPI:
register_io_dev = &register_io_dev_memmap;
fip_spec.offset = fip_spec.offset + STRATIX10_QSPI_DATA_BASE;
break;
default:
ERROR("Unsupported boot source\n");
panic();
break;
}
result = (*register_io_dev)(&boot_dev_con);
assert(result == 0);
result = register_io_dev_fip(&fip_dev_con);
assert(result == 0);
result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec,
&boot_dev_handle);
assert(result == 0);
result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
assert(result == 0);
if (boot_source == BOOT_SOURCE_SDMMC) {
partition_init(GPT_IMAGE_ID);
fip_spec.offset = get_partition_entry(a2)->start;
}
(void)result;
}
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int result;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
result = policy->check(policy->image_spec);
assert(result == 0);
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
return result;
}

2
plat/intel/soc/stratix10/platform.mk
View File

@ -34,7 +34,7 @@ BL2_SOURCES += \
drivers/gpio/gpio.c \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
plat/intel/soc/stratix10/bl2_plat_setup.c \
plat/intel/soc/stratix10/plat_storage.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
plat/intel/soc/common/soc/socfpga_handoff.c \