andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Tegra: sip: add VPR resize enabled check 

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
Anthony Zhou 2019-12-04 14:58:23 +08:00 committed by Varun Wadekar
parent 2561cb50f1
commit e9b9c2c830
6 changed files with 30 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
plat/nvidia/tegra/common/tegra_sip_calls.c
View File

@ -52,6 +52,12 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
switch (smc_fid) {
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
/* Check whether Video memory resize is enabled */
if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL)
!= MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED) {
ERROR("Video Memory Resize isn't enabled! \n");
SMC_RET1(handle, (uint64_t)-ENOTSUP);
}
/*
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)

17
plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
View File

@ -127,9 +127,16 @@ void tegra_memctrl_restore_settings(void)
if (video_mem_base != 0ULL) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
(uint32_t)video_mem_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)video_mem_base);
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
(uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(video_mem_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB,
(uint32_t)video_mem_size_mb);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (uint32_t)video_mem_size_mb);
/*
* MCE propagates the VideoMem configuration values across the
@ -367,6 +374,14 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
(uint32_t)(phys_base >> 32));
tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
/* Redundancy check for Video Protect setting */
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_LO)
== (uint32_t)phys_base);
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_BASE_HI)
== (uint32_t)(phys_base >> 32));
assert(tegra_mc_read_32(MC_VIDEO_PROTECT_SIZE_MB)
== (size_in_bytes >> 20));
/*
* MCE propagates the VideoMem configuration values across the
* CCPLEX.

2
plat/nvidia/tegra/include/t132/tegra_def.h
View File

@ -104,6 +104,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*******************************************************************************
* Tegra TZRAM constants

2
plat/nvidia/tegra/include/t186/tegra_def.h
View File

@ -163,6 +163,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the

2
plat/nvidia/tegra/include/t194/tegra_def.h
View File

@ -105,6 +105,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the

2
plat/nvidia/tegra/include/t210/tegra_def.h
View File

@ -240,6 +240,8 @@
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/* SMMU configuration registers*/
#define MC_SMMU_PPCS_ASID_0 0x270U