From e9e0b053ce756fa60afaedfa9eeb963a8aa87af3 Mon Sep 17 00:00:00 2001 From: Sandrine Bailleux Date: Tue, 3 Jun 2014 11:53:17 +0100 Subject: [PATCH] Juno: Enable non-secure accesses to the system timer This patch programs the CNTCTLBase.CNTNSAR to give non-secure access to timer frame 1. It also programs the CNTCTLBase.CNTACR1 to give access to all the timer registers in this frame. Change-Id: Ia10c9572a70bd5910031de1994116bb9314efd80 Conflicts: plat/juno/bl31_plat_setup.c plat/juno/platform.h --- plat/juno/bl31_plat_setup.c | 14 ++++++++++++++ plat/juno/juno_def.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c index 2eac0fb54..9489804dd 100644 --- a/plat/juno/bl31_plat_setup.c +++ b/plat/juno/bl31_plat_setup.c @@ -136,11 +136,25 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, ******************************************************************************/ void bl31_platform_setup(void) { + unsigned int reg_val; + mhu_secure_init(); /* Initialize the gic cpu and distributor interfaces */ gic_setup(); + /* Enable and initialize the System level generic timer */ + mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); + + /* Allow access to the System counter timer module */ + reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); + reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); + reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); + mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); + + reg_val = (1 << CNTNSAR_NS_SHIFT(1)); + mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); + /* Topologies are best known to the platform. */ plat_setup_topology(); } diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h index 6b3ba577b..96e16f0c9 100644 --- a/plat/juno/juno_def.h +++ b/plat/juno/juno_def.h @@ -75,6 +75,8 @@ /* Memory mapped Generic timer interfaces */ #define SYS_CNTCTL_BASE 0x2a430000 +#define SYS_CNTREAD_BASE 0x2a800000 +#define SYS_TIMCTL_BASE 0x2a810000 /* V2M motherboard system registers & offsets */ #define VE_SYSREGS_BASE 0x1c010000