Merge changes from topic "db/unsigned_long" into integration
* changes: Unsigned long should not be used as per coding guidelines SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
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commit
ea735643cb
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -23,7 +23,7 @@ void bl1_arch_setup(void)
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******************************************************************************/
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void bl1_arch_next_el_setup(void)
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{
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unsigned long next_sctlr;
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u_register_t next_sctlr;
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/* Use the same endianness than the current BL */
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next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
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@ -483,7 +483,7 @@ static int bl1_fwu_image_auth(unsigned int image_id,
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* Flush image_info to memory so that other
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* secure world images can see changes.
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*/
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flush_dcache_range((unsigned long)&image_desc->image_info,
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flush_dcache_range((uintptr_t)&image_desc->image_info,
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sizeof(image_info_t));
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INFO("BL1-FWU: Authentication was successful\n");
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@ -49,7 +49,7 @@ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
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bl2_mem_layout->total_base = bl1_mem_layout->total_base;
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bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
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flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
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flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
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}
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/*******************************************************************************
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@ -69,7 +69,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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uint32_t scr_el3;
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el3_state_t *state;
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gp_regs_t *gp_regs;
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unsigned long sctlr_elx, actlr_elx;
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u_register_t sctlr_elx, actlr_elx;
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assert(ctx != NULL);
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