From eeb5a7b595ebe938c3cf720507c5474a8ea3153b Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 3 Sep 2019 21:08:51 +0300 Subject: [PATCH 1/2] SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64 AArch64 System register SCTLR_EL1[31:0] is architecturally mapped to AArch32 System register SCTLR[31:0] AArch64 System register ACTLR_EL1[31:0] is architecturally mapped to AArch32 System register ACTLR[31:0]. `u_register_t` should be used when it's important to store the contents of a register in its native size Signed-off-by: Deepika Bhavnani Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779 --- lib/el3_runtime/aarch64/context_mgmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 446d9da92..a05ee5a6e 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -69,7 +69,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) uint32_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; - unsigned long sctlr_elx, actlr_elx; + u_register_t sctlr_elx, actlr_elx; assert(ctx != NULL); From ee006a79f622b39a35beaaf95d7b42b7078823f8 Mon Sep 17 00:00:00 2001 From: Deepika Bhavnani Date: Tue, 3 Sep 2019 21:51:09 +0300 Subject: [PATCH 2/2] Unsigned long should not be used as per coding guidelines We should either change them to `unsigned int` or `unsigned long long` when the size of the variable is the same in AArch64 and AArch32 or to `u_register_t` if it is supposed to be 32 bit wide in AArch32 and 64 bit wide in AArch64. Signed-off-by: Deepika Bhavnani Change-Id: I80e2a6edb33248ee88be395829abbd4c36c89abe --- bl1/aarch64/bl1_arch_setup.c | 4 ++-- bl1/bl1_fwu.c | 2 +- bl1/bl1_main.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 624bd80f2..0a1cb304a 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ void bl1_arch_setup(void) ******************************************************************************/ void bl1_arch_next_el_setup(void) { - unsigned long next_sctlr; + u_register_t next_sctlr; /* Use the same endianness than the current BL */ next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index d222b9c52..48f08d2ca 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -483,7 +483,7 @@ static int bl1_fwu_image_auth(unsigned int image_id, * Flush image_info to memory so that other * secure world images can see changes. */ - flush_dcache_range((unsigned long)&image_desc->image_info, + flush_dcache_range((uintptr_t)&image_desc->image_info, sizeof(image_info_t)); INFO("BL1-FWU: Authentication was successful\n"); diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index d44b46dc9..b882a07e5 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -48,7 +48,7 @@ void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, bl2_mem_layout->total_base = bl1_mem_layout->total_base; bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; - flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); + flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); } /*******************************************************************************