From ecf70f7bdbf79bd2923ec5b14b933ba4c8e3ee59 Mon Sep 17 00:00:00 2001 From: Vikram Kanigiri Date: Thu, 21 Jan 2016 14:08:15 +0000 Subject: [PATCH 1/3] Re-factor definition of some macros on ARM platforms This patch moves the definition of some macros used only on ARM platforms from common headers to platform specific headers. It also forces all ARM standard platforms to have distinct definitions (even if they are usually the same). 1. `PLAT_ARM_TZC_BASE` and `PLAT_ARM_NSTIMER_FRAME_ID` have been moved from `css_def.h` to `platform_def.h`. 2. `MHU_BASE` used in CSS platforms is moved from common css_def.h to platform specific header `platform_def.h` on Juno and renamed as `PLAT_ARM_MHU_BASE`. 3. To cater for different sizes of BL images, new macros like `PLAT_ARM_MAX_BL31_SIZE` have been created for each BL image. All ARM platforms need to define them for each image. Change-Id: I9255448bddfad734b387922aa9e68d2117338c3f --- include/plat/arm/common/arm_def.h | 27 +++++------------ include/plat/arm/css/common/css_def.h | 7 +---- plat/arm/board/fvp/include/platform_def.h | 28 +++++++++++++++++- plat/arm/board/juno/include/platform_def.h | 34 +++++++++++++++++++++- plat/arm/css/common/css_mhu.c | 17 ++++++----- 5 files changed, 78 insertions(+), 35 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index b2db6160d..4c8435607 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -239,44 +239,31 @@ #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + PLAT_ARM_TRUSTED_ROM_SIZE) /* - * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using - * the current BL1 RW debug size plus a little space for growth. + * Put BL1 RW at the top of the Trusted SRAM. */ -#if TRUSTED_BOARD_BOOT #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ ARM_BL_RAM_SIZE - \ - 0x9000) -#else -#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ - ARM_BL_RAM_SIZE - \ - 0x6000) -#endif + PLAT_ARM_MAX_BL1_RW_SIZE) #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) /******************************************************************************* * BL2 specific defines. ******************************************************************************/ /* - * Put BL2 just below BL31. BL2_BASE is calculated using the current BL2 debug - * size plus a little space for growth. + * Put BL2 just below BL31. */ -#if TRUSTED_BOARD_BOOT -#define BL2_BASE (BL31_BASE - 0x1D000) -#else -#define BL2_BASE (BL31_BASE - 0xC000) -#endif +#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) #define BL2_LIMIT BL31_BASE /******************************************************************************* * BL31 specific defines. ******************************************************************************/ /* - * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the - * current BL31 debug size plus a little space for growth. + * Put BL31 at the top of the Trusted SRAM. */ #define BL31_BASE (ARM_BL_RAM_BASE + \ ARM_BL_RAM_SIZE - \ - 0x1D000) + PLAT_ARM_MAX_BL31_SIZE) #define BL31_PROGBITS_LIMIT BL1_RW_BASE #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index c900278b5..43d1c54f7 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -45,7 +45,6 @@ /* Following covers CSS Peripherals excluding NSROM and NSRAM */ #define CSS_DEVICE_BASE 0x20000000 #define CSS_DEVICE_SIZE 0x0e000000 -#define MHU_BASE 0x2b1f0000 #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x00008000 @@ -125,10 +124,6 @@ /* TZC related constants */ #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL -#define PLAT_ARM_TZC_BASE 0x2a4a0000 - -/* System timer related constants */ -#define PLAT_ARM_NSTIMER_FRAME_ID 1 /* Trusted mailbox base address common to all CSS */ #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 0d671dc03..9c82cbfa2 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -144,4 +144,30 @@ #define PLAT_ARM_G0_IRQS ARM_G0_IRQS +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 +#else +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 924eb0ab7..99de7617b 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -76,7 +76,11 @@ #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + /* TZC related constants */ +#define PLAT_ARM_TZC_BASE 0x2a4a0000 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ @@ -99,6 +103,9 @@ #define PLAT_ARM_GICH_BASE 0x2c04f000 #define PLAT_ARM_GICV_BASE 0x2c06f000 +/* MHU related constants */ +#define PLAT_CSS_MHU_BASE 0x2b1f0000 + /* * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 * terminology. On a GICv2 system or mode, the lists will be merged and treated @@ -124,5 +131,30 @@ /* CSS SoC NIC-400 Global Programmers View (GPV) */ #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 +#else +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/arm/css/common/css_mhu.c b/plat/arm/css/common/css_mhu.c index b1714e222..265d6c25c 100644 --- a/plat/arm/css/common/css_mhu.c +++ b/plat/arm/css/common/css_mhu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "css_mhu.h" @@ -66,24 +67,26 @@ void mhu_secure_message_start(unsigned int slot_id) arm_lock_get(); /* Make sure any previous command has finished */ - while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id)) + while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & + (1 << slot_id)) ; } void mhu_secure_message_send(unsigned int slot_id) { assert(slot_id <= MHU_MAX_SLOT_ID); - assert(!(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id))); + assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & + (1 << slot_id))); /* Send command to SCP */ - mmio_write_32(MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); + mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); } uint32_t mhu_secure_message_wait(void) { /* Wait for response from SCP */ uint32_t response; - while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT))) + while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) ; return response; @@ -97,7 +100,7 @@ void mhu_secure_message_end(unsigned int slot_id) * Clear any response we got by writing one in the relevant slot bit to * the CLEAR register */ - mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); + mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); arm_lock_release(); } @@ -111,7 +114,7 @@ void mhu_secure_init(void) * as a stale or garbage value would make us think it's a message we've * already sent. */ - assert(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) == 0); + assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); } void plat_arm_pwrc_setup(void) From 421295a017d6c2378376a14cc13b5076129d347b Mon Sep 17 00:00:00 2001 From: Vikram Kanigiri Date: Thu, 12 Nov 2015 17:22:16 +0000 Subject: [PATCH 2/3] Add support for SSC_VERSION register on CSS platforms Each ARM Compute Subsystem based platform implements a System Security Control (SSC) Registers Unit. The SSC_VERSION register inside it carries information to identify the platform. This enables ARM Trusted Firmware to compile in support for multiple ARM platforms and choose one at runtime. This patch adds macros to enable access to this register. Each platform is expected to export its PART_NUMBER separately. Additionally, it also adds juno part number. Change-Id: I2b1d5f5b65a9c7b76c6f64480cc7cf0aef019422 --- include/plat/arm/css/common/css_def.h | 29 +++++++++++++++++++++++++++ plat/arm/board/juno/juno_def.h | 3 ++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 43d1c54f7..256f0d8d8 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -102,6 +102,35 @@ CSS_DEVICE_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +/* Platform ID address */ +#define SSC_VERSION_OFFSET 0x040 + +#define SSC_VERSION_CONFIG_SHIFT 28 +#define SSC_VERSION_MAJOR_REV_SHIFT 24 +#define SSC_VERSION_MINOR_REV_SHIFT 20 +#define SSC_VERSION_DESIGNER_ID_SHIFT 12 +#define SSC_VERSION_PART_NUM_SHIFT 0x0 +#define SSC_VERSION_CONFIG_MASK 0xf +#define SSC_VERSION_MAJOR_REV_MASK 0xf +#define SSC_VERSION_MINOR_REV_MASK 0xf +#define SSC_VERSION_DESIGNER_ID_MASK 0xff +#define SSC_VERSION_PART_NUM_MASK 0xfff + +#ifndef __ASSEMBLY__ + +/* SSC_VERSION related accessors */ + +/* Returns the part number of the platform */ +#define GET_SSC_VERSION_PART_NUM(val) \ + (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ + SSC_VERSION_PART_NUM_MASK) + +/* Returns the configuration number of the platform */ +#define GET_SSC_VERSION_CONFIG(val) \ + (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ + SSC_VERSION_CONFIG_MASK) + +#endif /* __ASSEMBLY__ */ /************************************************************************* * Required platform porting definitions common to all diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h index 1f367f274..f4e225996 100644 --- a/plat/arm/board/juno/juno_def.h +++ b/plat/arm/board/juno/juno_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -50,6 +50,7 @@ #define PSRAM_BASE 0x14000000 #define PSRAM_SIZE 0x02000000 +#define JUNO_SSC_VER_PART_NUM 0x030 /******************************************************************************* * TZC-400 related constants From 65cb1c4c285c0701217ee53d1b6b4a1f68ccbd35 Mon Sep 17 00:00:00 2001 From: Vikram Kanigiri Date: Thu, 12 Nov 2015 18:52:34 +0000 Subject: [PATCH 3/3] Add API to return memory map on ARM platforms Functions to configure the MMU in S-EL1 and EL3 on ARM platforms expect each platform to export its memory map in the `plat_arm_mmap` data structure. This approach does not scale well in case the memory map cannot be determined until runtime. To cater for this possibility, this patch introduces the plat_arm_get_mmap() API. It returns a reference to the `plat_arm_mmap` by default but can be overridden by a platform if required. Change-Id: Idae6ad8fdf40cdddcd8b992abc188455fa047c74 --- include/plat/arm/common/plat_arm.h | 9 ++------- plat/arm/common/aarch64/arm_common.c | 16 +++++++++++++--- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 3b6a04ba3..a7c34afc4 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -37,11 +37,6 @@ #include #include -/* - * Extern declarations common to ARM standard platforms - */ -extern const mmap_region_t plat_arm_mmap[]; - #define ARM_CASSERT_MMAP \ CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ <= MAX_MMAP_REGIONS, \ @@ -204,6 +199,6 @@ int plat_arm_get_alt_image_source( uintptr_t *dev_handle, uintptr_t *image_spec); unsigned int plat_arm_calc_core_pos(u_register_t mpidr); - +const mmap_region_t *plat_arm_get_mmap(void); #endif /* __PLAT_ARM_H__ */ diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c index a211f16d3..02062861f 100644 --- a/plat/arm/common/aarch64/arm_common.c +++ b/plat/arm/common/aarch64/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,6 +35,7 @@ #include #include +extern const mmap_region_t plat_arm_mmap[]; static const int cci_map[] = { PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX, @@ -43,6 +44,7 @@ static const int cci_map[] = { /* Weak definitions may be overridden in specific ARM standard platform */ #pragma weak plat_get_ns_image_entrypoint +#pragma weak plat_arm_get_mmap /******************************************************************************* @@ -67,7 +69,7 @@ static const int cci_map[] = { mmap_add_region(coh_start, coh_start, \ coh_limit - coh_start, \ MT_DEVICE | MT_RW | MT_SECURE); \ - mmap_add(plat_arm_mmap); \ + mmap_add(plat_arm_get_mmap()); \ init_xlat_tables(); \ \ enable_mmu_el##_el(0); \ @@ -85,7 +87,7 @@ static const int cci_map[] = { mmap_add_region(ro_start, ro_start, \ ro_limit - ro_start, \ MT_MEMORY | MT_RO | MT_SECURE); \ - mmap_add(plat_arm_mmap); \ + mmap_add(plat_arm_get_mmap()); \ init_xlat_tables(); \ \ enable_mmu_el##_el(0); \ @@ -161,3 +163,11 @@ void arm_configure_sys_timer(void) reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); } + +/******************************************************************************* + * Returns ARM platform specific memory map regions. + ******************************************************************************/ +const mmap_region_t *plat_arm_get_mmap(void) +{ + return plat_arm_mmap; +}