intel: Fix argument type for mailbox driver
This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch. Revert changing argument type from uint32_t to uint64_t to fix incompatible cast issue. Fix said bug by using intermediate uint32_t array as a more appropriate solution. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d
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@ -126,9 +126,9 @@ int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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void mailbox_set_qspi_open(void);
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void mailbox_set_qspi_direct(void);
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args,
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent, uint32_t *response, int resp_len);
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent);
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int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
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int mailbox_get_qspi_clock(void);
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@ -140,7 +140,7 @@ int intel_mailbox_is_fpga_not_ready(void);
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_update(uint64_t *flash_offset);
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int mailbox_hps_stage_notify(uint64_t execution_stage);
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int mailbox_rsu_update(uint32_t *flash_offset);
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int mailbox_hps_stage_notify(uint32_t execution_stage);
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#endif /* SOCFPGA_MBOX_H */
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@ -11,7 +11,7 @@
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#include "socfpga_mailbox.h"
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#include "socfpga_sip_svc.h"
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static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint64_t *args,
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static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
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int len)
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{
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uint32_t cmd_free_offset;
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@ -167,7 +167,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response,
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}
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}
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
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int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent)
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{
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if (urgent)
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@ -184,7 +184,7 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
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return 0;
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}
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args,
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int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
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int len, int urgent, uint32_t *response, int resp_len)
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{
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int status = 0;
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@ -252,7 +252,7 @@ int mailbox_get_qspi_clock(void)
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void mailbox_qspi_set_cs(int device_select)
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{
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uint64_t cs_setting = device_select;
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uint32_t cs_setting = device_select;
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/* QSPI device select settings at 31:28 */
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cs_setting = (cs_setting << 28);
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@ -304,13 +304,13 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len)
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return ret;
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}
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int mailbox_rsu_update(uint64_t *flash_offset)
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int mailbox_rsu_update(uint32_t *flash_offset)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
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flash_offset, 2, 0, NULL, 0);
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}
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int mailbox_hps_stage_notify(uint64_t execution_stage)
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int mailbox_hps_stage_notify(uint32_t execution_stage)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY,
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&execution_stage, 1, 0, NULL, 0);
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@ -134,8 +134,13 @@ extern uint64_t intel_rsu_update_address;
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static void __dead2 socfpga_system_reset(void)
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{
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uint32_t addr_buf[2];
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memcpy(addr_buf, &intel_rsu_update_address,
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sizeof(intel_rsu_update_address));
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if (intel_rsu_update_address)
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mailbox_rsu_update(&intel_rsu_update_address);
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mailbox_rsu_update(addr_buf);
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else
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mailbox_reset_cold();
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@ -61,7 +61,7 @@ struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
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static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
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{
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uint64_t args[3];
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uint32_t args[3];
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while (max_blocks > 0 && buffer->size > buffer->size_written) {
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args[0] = (1<<8);
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@ -385,7 +385,7 @@ static uint32_t intel_rsu_update(uint64_t update_address)
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_notify(uint64_t execution_stage)
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static uint32_t intel_rsu_notify(uint32_t execution_stage)
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{
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if (mailbox_hps_stage_notify(execution_stage) < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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@ -404,7 +404,7 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
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}
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/* Mailbox services */
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static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint64_t *args, int len,
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static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len,
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int urgent, uint32_t *response,
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int resp_len, int *mbox_status,
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int *len_in_resp)
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@ -542,7 +542,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
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case INTEL_SIP_SMC_MBOX_SEND_CMD:
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x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
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x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
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status = intel_mbox_send_cmd(x1, (uint64_t *)x2, x3, x4,
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status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
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(uint32_t *)x5, x6, &mbox_status,
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&len_in_resp);
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SMC_RET4(handle, status, mbox_status, x5, len_in_resp);
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