zynqmp: pm_service: use zynqmp_ipi APIs
Use zynqmp_ipi APIs to access IPI registers in pm_service. As the zynqmp_ipi APIs doesn't cover IPI buffers, the pm_ipi in pm_service will still directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
This commit is contained in:
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e8ffe79d06
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ebc05162ae
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -542,7 +542,6 @@ enum pm_ret_status pm_get_chipid(uint32_t *value)
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*/
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*/
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void pm_get_callbackdata(uint32_t *data, size_t count)
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void pm_get_callbackdata(uint32_t *data, size_t count)
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{
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{
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pm_ipi_buff_read_callb(data, count);
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pm_ipi_buff_read_callb(data, count);
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pm_ipi_irq_clear();
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pm_ipi_irq_clear(primary_proc);
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}
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}
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@ -21,13 +21,13 @@
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/**
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/**
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* pm_ipi - struct for capturing IPI-channel specific info
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* pm_ipi - struct for capturing IPI-channel specific info
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* @mask mask for enabling/disabling and triggering the IPI
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* @apu_ipi_id APU IPI agent ID
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* @base base address for IPI
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* @pmu_ipi_id PMU Agent ID
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* @buffer_base base address for payload buffer
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* @buffer_base base address for payload buffer
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*/
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*/
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struct pm_ipi {
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struct pm_ipi {
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const unsigned int mask;
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const uint32_t apu_ipi_id;
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const uintptr_t base;
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const uint32_t pmu_ipi_id;
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const uintptr_t buffer_base;
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const uintptr_t buffer_base;
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};
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};
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -8,28 +8,17 @@
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#include <bakery_lock.h>
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#include <bakery_lock.h>
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#include <mmio.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform.h>
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#include "../zynqmp_ipi.h"
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#include "../zynqmp_private.h"
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#include "../zynqmp_private.h"
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#include "pm_ipi.h"
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#include "pm_ipi.h"
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/* IPI message buffers */
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/* IPI message buffers */
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#define IPI_BUFFER_BASEADDR 0xFF990000U
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#define IPI_BUFFER_BASEADDR 0xFF990000U
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#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U)
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#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U)
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U)
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#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U)
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#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U)
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#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U)
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#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
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#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
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#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U
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#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U
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#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
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#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
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#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U
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#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U
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#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U
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#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U
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#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U
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#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U
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#define IPI_BUFFER_MAX_WORDS 8
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#define IPI_BUFFER_MAX_WORDS 8
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@ -37,75 +26,32 @@
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/* IPI Base Address */
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#define IPI_BASEADDR 0XFF300000
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/* APU's IPI registers */
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#define IPI_APU_ISR (IPI_BASEADDR + 0X00000010)
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#define IPI_APU_IER (IPI_BASEADDR + 0X00000018)
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#define IPI_APU_IDR (IPI_BASEADDR + 0X0000001C)
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#define IPI_APU_IXR_PMU_0_MASK (1 << 16)
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#define IPI_TRIG_OFFSET 0
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#define IPI_OBS_OFFSET 4
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/* Power Management IPI interrupt number */
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#define PM_INT_NUM 0
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#define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000))
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#define IPI_PMU_PM_INT_MASK (IPI_APU_IXR_PMU_0_MASK << PM_INT_NUM)
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#if (PM_INT_NUM < 0 || PM_INT_NUM > 3)
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#error PM_INT_NUM value out of range
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#endif
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#define IPI_APU_MASK 1U
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DEFINE_BAKERY_LOCK(pm_secure_lock);
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DEFINE_BAKERY_LOCK(pm_secure_lock);
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const struct pm_ipi apu_ipi = {
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const struct pm_ipi apu_ipi = {
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.mask = IPI_APU_MASK,
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.apu_ipi_id = IPI_ID_APU,
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.base = IPI_BASEADDR,
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.pmu_ipi_id = IPI_ID_PMU0,
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.buffer_base = IPI_BUFFER_APU_BASE,
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.buffer_base = IPI_BUFFER_APU_BASE,
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};
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};
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/**
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/**
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* pm_ipi_init() - Initialize IPI peripheral for communication with PMU
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* pm_ipi_init() - Initialize IPI peripheral for communication with PMU
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*
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*
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* @proc Pointer to the processor who is initiating request
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* @return On success, the initialization function must return 0.
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* @return On success, the initialization function must return 0.
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* Any other return value will cause the framework to ignore
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* Any other return value will cause the framework to ignore
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* the service
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* the service
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*
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*
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* Called from pm_setup initialization function
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* Called from pm_setup initialization function
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*/
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*/
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int pm_ipi_init(void)
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int pm_ipi_init(const struct pm_proc *proc)
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{
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{
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bakery_lock_init(&pm_secure_lock);
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bakery_lock_init(&pm_secure_lock);
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ipi_mb_open(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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/* IPI Interrupts Clear & Disable */
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mmio_write_32(IPI_APU_ISR, 0xffffffff);
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mmio_write_32(IPI_APU_IDR, 0xffffffff);
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return 0;
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return 0;
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}
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}
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/**
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* pm_ipi_wait() - wait for pmu to handle request
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* @proc proc which is waiting for PMU to handle request
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*/
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static enum pm_ret_status pm_ipi_wait(const struct pm_proc *proc)
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{
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int status;
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/* Wait until previous interrupt is handled by PMU */
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do {
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status = mmio_read_32(proc->ipi->base + IPI_OBS_OFFSET) &
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IPI_PMU_PM_INT_MASK;
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/* TODO: 1) Use timer to add delay between read attempts */
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/* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */
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} while (status);
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return PM_RET_SUCCESS;
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}
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/**
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/**
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* pm_ipi_send_common() - Sends IPI request to the PMU
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* pm_ipi_send_common() - Sends IPI request to the PMU
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* @proc Pointer to the processor who is initiating request
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* @proc Pointer to the processor who is initiating request
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_REQ_OFFSET;
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IPI_BUFFER_REQ_OFFSET;
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/* Wait until previous interrupt is handled by PMU */
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pm_ipi_wait(proc);
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/* Write payload into IPI buffer */
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/* Write payload into IPI buffer */
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for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) {
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for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) {
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mmio_write_32(buffer_base + offset, payload[i]);
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mmio_write_32(buffer_base + offset, payload[i]);
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offset += PAYLOAD_ARG_SIZE;
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offset += PAYLOAD_ARG_SIZE;
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}
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}
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/* Generate IPI to PMU */
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/* Generate IPI to PMU */
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mmio_write_32(proc->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK);
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ipi_mb_notify(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id, 1);
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return PM_RET_SUCCESS;
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return PM_RET_SUCCESS;
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}
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}
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_RESP_OFFSET;
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IPI_BUFFER_RESP_OFFSET;
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pm_ipi_wait(proc);
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/*
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/*
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* Read response from IPI buffer
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* Read response from IPI buffer
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* buf-0: success or error+reason
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* buf-0: success or error+reason
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return ret;
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return ret;
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}
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}
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void pm_ipi_irq_enable(void)
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void pm_ipi_irq_enable(const struct pm_proc *proc)
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{
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{
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mmio_write_32(IPI_APU_IER, IPI_APU_IXR_PMU_0_MASK);
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ipi_mb_enable_irq(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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}
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}
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void pm_ipi_irq_disable(void)
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void pm_ipi_irq_clear(const struct pm_proc *proc)
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{
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{
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mmio_write_32(IPI_APU_IDR, IPI_APU_IXR_PMU_0_MASK);
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ipi_mb_ack(proc->ipi->apu_ipi_id, proc->ipi->pmu_ipi_id);
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}
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void pm_ipi_irq_clear(void)
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{
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mmio_write_32(IPI_APU_ISR, IPI_APU_IXR_PMU_0_MASK);
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}
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}
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/*
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include "pm_common.h"
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#include "pm_common.h"
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int pm_ipi_init(void);
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int pm_ipi_init(const struct pm_proc *proc);
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enum pm_ret_status pm_ipi_send(const struct pm_proc *proc,
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enum pm_ret_status pm_ipi_send(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT]);
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uint32_t payload[PAYLOAD_ARG_CNT]);
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uint32_t payload[PAYLOAD_ARG_CNT],
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uint32_t payload[PAYLOAD_ARG_CNT],
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unsigned int *value, size_t count);
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unsigned int *value, size_t count);
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void pm_ipi_buff_read_callb(unsigned int *value, size_t count);
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void pm_ipi_buff_read_callb(unsigned int *value, size_t count);
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void pm_ipi_irq_enable(void);
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void pm_ipi_irq_enable(const struct pm_proc *proc);
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void pm_ipi_irq_disable(void);
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void pm_ipi_irq_clear(const struct pm_proc *proc);
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void pm_ipi_irq_clear(void);
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#endif /* _PM_IPI_H_ */
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#endif /* _PM_IPI_H_ */
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/*
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/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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*/
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*/
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int pm_setup(void)
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int pm_setup(void)
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{
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{
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int status;
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int status, ret;
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if (!zynqmp_is_pmu_up())
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if (!zynqmp_is_pmu_up())
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return -ENODEV;
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return -ENODEV;
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status = pm_ipi_init();
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status = pm_ipi_init(primary_proc);
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if (status == 0)
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if (status >= 0) {
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INFO("BL31: PM Service Init Complete: API v%d.%d\n",
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INFO("BL31: PM Service Init Complete: API v%d.%d\n",
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PM_VERSION_MAJOR, PM_VERSION_MINOR);
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PM_VERSION_MAJOR, PM_VERSION_MINOR);
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else
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ret = 0;
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} else {
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INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
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INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
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ret = status;
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}
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pm_down = status;
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pm_down = status;
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return status;
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return ret;
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}
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}
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/**
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/**
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* Even if we were wrong, it would not enable the IRQ in
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* Even if we were wrong, it would not enable the IRQ in
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* the GIC.
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* the GIC.
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*/
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*/
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pm_ipi_irq_enable();
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pm_ipi_irq_enable(primary_proc);
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SMC_RET1(handle, (uint64_t)ret |
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SMC_RET1(handle, (uint64_t)ret |
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((uint64_t)pm_ctx.api_version << 32));
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((uint64_t)pm_ctx.api_version << 32));
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