From c5e0b3b06f4c715b1ab81b0c099939478b9617f7 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 29 Jul 2018 11:53:32 +0300 Subject: [PATCH 01/17] docs: marvell: Update build manual Update build manual - remove irrelevant platforms and environemnt variables - add links to BLE and mv_ddr Github repositories Change-Id: Ie389c61f014751cdc0459b3f78c70ede694d27b8 Signed-off-by: Konstantin Porotchkin --- docs/marvell/build.txt | 94 ++++++++++++++++++++++++------------------ 1 file changed, 55 insertions(+), 39 deletions(-) diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt index 63a40a8d8..b354ab6ab 100644 --- a/docs/marvell/build.txt +++ b/docs/marvell/build.txt @@ -22,14 +22,14 @@ Build Instructions u-boot.bin should be used and not u-boot-spl.bin - Set MSS/SCP image path (mandatory only for Armada80x0 and Aramada8xxy):: + Set MSS/SCP image path (mandatory only for Armada80x0):: > export SCP_BL2=path/to/mrvl_scp_bl2*.img (3) Armada-37x0 build requires WTP tools installation. - See below in the section "Tools Installation for Armada37x0 Builds". - Install ARM 32-bit cross compiler, which is required by building WTMI image for CM3:: + See below in the section "Tools and external components installation". + Install ARM 32-bit cross compiler, which is required for building WTMI image for CM3:: > sudo apt-get install gcc-arm-linux-gnueabi @@ -42,6 +42,8 @@ Build Instructions There are several build options: - DEBUG: default is without debug information (=0). in order to enable it use DEBUG=1 + Must be disabled when building UART recovery images due to current console driver + implementation that is not compatible with Xmodem protocol used for boot image download. - LOG_LEVEL: defines the level of logging which will be purged to the default output port. @@ -55,13 +57,14 @@ Build Instructions - USE_COHERENT_MEM: This flag determines whether to include the coherent memory region in the BL memory map or not. - -LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1). + - LLC_ENABLE: Flag defining the LLC (L3) cache state. The cache is enabled by default (LLC_ENABLE=1). - MARVELL_SECURE_BOOT: build trusted(=1)/non trusted(=0) image, default is non trusted. - BLE_PATH: - Points to BLE (Binary ROM extension) sources folder. Only required for A8K and A8K+ builds. + Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds. The parameter is optional, its default value is "ble". + For the BLE source location, check the section "Tools and external components installation" - MV_DDR_PATH: For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0, @@ -70,6 +73,7 @@ Build Instructions The parameter is optional for A7/8K, when this parameter is not set, the mv_ddr sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter is necessary for A37x0. + For the mv_ddr source location, check the section "Tools and external components installation" - DDR_TOPOLOGY: For Armada37x0 only, the DDR topology map index/name, default is 0. Supported Options: @@ -88,14 +92,14 @@ Build Instructions - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz - BOOTDEV: For Armada37x0 only, the flash boot device, default is SPINOR, - Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA: + Currently, Armada37x0 only supports SPINOR, SPINAND, EMMCNORM and SATA: - - SPINOR - SPI NOR flash boot - - SPINAND - SPI NAND flash boot - - EMMCNORM - eMMC Download Mode - Download boot loader or program code from eMMC flash into CM3 or CA53 - Requires full initialization and command sequence - - SATA - SATA device boot + - SPINOR - SPI NOR flash boot + - SPINAND - SPI NAND flash boot + - EMMCNORM - eMMC Download Mode + Download boot loader or program code from eMMC flash into CM3 or CA53 + Requires full initialization and command sequence + - SATA - SATA device boot - PARTNUM: For Armada37x0 only, the boot partition number, default is 0. To boot from eMMC, the value should be aligned with the parameter in U-Boot with name of CONFIG_SYS_MMC_ENV_PART, whose @@ -106,45 +110,35 @@ Build Instructions nothing, an image which supports EFUSE or a customized CM3 firmware binary. The default image is wtmi.bin that built from sources in WTP folder, which is the next option. If the default image is OK, then this option should be skipped. + - WTP: For Armada37x0 only, use this parameter to point to wtptools source code directory, which can be found as a3700_utils.zip in the release. Usage example: WTP=/path/to/a3700_utils - - CP_NUM: Total amount of CPs (South Bridge) chips wired to the interconnected APs. - When the parameter is omitted, the build is uses the default number of CPs equal to 2. - The parameter is valid for Armada 8K-plus SoC family (PLAT=a8xxy) and results in a build of images - suitable for a8xxY SoC, where "Y" is a number of connected CPs and "xx" is a number of CPU cores. - Valid values with CP_NUM is in a range of 0 to 8. - The CPs defined by this parameter are evenly distributed across interconnected APs that in turn - are dynamically detected. For instance, if the CP_NUM=6 and the TF-A detects 2 interconnected - APs, each AP assumed to have 3 attached CPs. With the same amount of APs and CP_NUM=3, the AP0 - will have 2 CPs connected and AP1 - a just single CP. - For example, in order to build the image in debug mode with log level up to 'notice' level run:: > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT= all fip And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level, - the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR3 2CS, + the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS, the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command line is as following:: > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 SECURE=0 CLOCKSPRESET=CPU_1000_DDR_800 \ - DDR_TOPOLOGY=2 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip + DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip Supported MARVELL_PLATFORM are: - - a3700 + - a3700 (for both A3720 DB and EspressoBin) - a70x0 - a70x0_amc (for AMC board) - - a70x0_cust (for customers) - a80x0 - a80x0_mcbin (for MacciatoBin) Special Build Flags -------------------- - PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build - atf. In order to build uart recovery image this operation should be disabled for a70x0 and a80x0 - because of hardware limitation(boot from secondary image can interrupt uart recovery process). + atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0 + because of hardware limitation (boot from secondary image can interrupt UART recovery process). This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file (for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide: @@ -160,22 +154,44 @@ Marvell's TF-A compilation generates 7 files: - bl31.bin - BL31 image - fip.bin - FIP image (contains BL2, BL31 & BL33 (U-Boot) images) - boot-image.bin - TF-A image (contains BL1 and FIP images) - - flash-image.bin - Image which contains boot-image.bin and SPL image; should be placed on the boot flash/device. + - flash-image.bin - Image which contains boot-image.bin and SPL image; + should be placed on the boot flash/device. -Tools Installation for Armada37x0 Builds ------------------------------------------ -Install a cross GNU ARM tool chain for building the WTMI binary. -Any cross GNU ARM tool chain that is able to build ARM Cortex M3 binaries -is suitable. +Tools and external components installation +========================================== -On Debian/Uboot hosts the default GNU ARM tool chain can be installed -using the following command:: +Armada37x0 Builds require installation of 3 components +------------------------------------------------------- + +(1) ARM cross compiler capable of building images for the service CPU (CM3). + This component is usually included in the Linux host packages. + On Debian/Uboot hosts the default GNU ARM tool chain can be installed + using the following command:: > sudo apt-get install gcc-arm-linux-gnueabi -If required, the default tool chain prefix "arm-linux-gnueabi-" can be -overwritten using the environment variable CROSS_CM3. -Example for BASH shell:: + Only if required, the default tool chain prefix "arm-linux-gnueabi-" can be + overwritten using the environment variable CROSS_CM3. + Example for BASH shell:: > export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi + +(2) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch):: + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + +(3) Armada3700 tools available at the following repository (use the latest release branch):: + https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git + +Armada70x0 and Armada80x0 Builds require installation of 2 components +--------------------------------------------------------------------- + +(1) DDR initialization library sources (mv_ddr) available at the following repository + (use the "mv_ddr-armada-atf-mainline" branch):: + https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git + +(2) BLE sources available at the following repository (use the "atf-mainline" branch):: + https://github.com/MarvellEmbeddedProcessors/ble-marvell.git + + From 94d6dd677bd2b0837810909af80f8e9702bbd841 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 29 Jul 2018 13:30:51 +0300 Subject: [PATCH 02/17] plat: marvell: rename common include file Rename a8k_common.h to armada_common.h to keep the same header name across all other Marvell Armada platforms. This is especially useful since various Marvell platforms may use common platform files and share the driver modules. Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef Signed-off-by: Konstantin Porotchkin --- drivers/marvell/amb_adec.c | 2 +- drivers/marvell/ccu.c | 2 +- drivers/marvell/gwin.c | 2 +- drivers/marvell/i2c/a8k_i2c.c | 2 +- drivers/marvell/io_win.c | 2 +- drivers/marvell/iob.c | 2 +- .../plat/marvell/a8k/common/{a8k_common.h => armada_common.h} | 0 plat/marvell/a8k/a70x0/board/marvell_plat_config.c | 2 +- plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c | 2 +- plat/marvell/a8k/a80x0/board/marvell_plat_config.c | 3 ++- plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c | 3 ++- plat/marvell/a8k/common/mss/mss_bl2_setup.c | 2 +- plat/marvell/a8k/common/plat_bl31_setup.c | 2 +- plat/marvell/a8k/common/plat_ble_setup.c | 2 +- plat/marvell/a8k/common/plat_pm.c | 2 +- 15 files changed, 16 insertions(+), 14 deletions(-) rename include/plat/marvell/a8k/common/{a8k_common.h => armada_common.h} (100%) diff --git a/drivers/marvell/amb_adec.c b/drivers/marvell/amb_adec.c index 3fb2f3890..16fe772da 100644 --- a/drivers/marvell/amb_adec.c +++ b/drivers/marvell/amb_adec.c @@ -7,7 +7,7 @@ /* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */ -#include +#include #include #include #include diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c index 1502c3f8b..acb1c00c0 100644 --- a/drivers/marvell/ccu.c +++ b/drivers/marvell/ccu.c @@ -7,7 +7,7 @@ /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ -#include +#include #include #include #include diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c index b5705f7a4..a4743eb5e 100644 --- a/drivers/marvell/gwin.c +++ b/drivers/marvell/gwin.c @@ -7,7 +7,7 @@ /* GWIN unit device driver for Marvell AP810 SoC */ -#include +#include #include #include #include diff --git a/drivers/marvell/i2c/a8k_i2c.c b/drivers/marvell/i2c/a8k_i2c.c index 737dd0a72..72a773162 100644 --- a/drivers/marvell/i2c/a8k_i2c.c +++ b/drivers/marvell/i2c/a8k_i2c.c @@ -442,7 +442,7 @@ static int marvell_i2c_unstuck(int ret) void i2c_init(void *i2c_base) { /* For I2C speed and slave address, now we do not set them since - * we just provide the working speed and slave address in plat_def.h + * we just provide the working speed and slave address in mvebu_def.h * for i2c_init */ base = (struct marvell_i2c_regs *)i2c_base; diff --git a/drivers/marvell/io_win.c b/drivers/marvell/io_win.c index 40b198212..c0424e086 100644 --- a/drivers/marvell/io_win.c +++ b/drivers/marvell/io_win.c @@ -7,7 +7,7 @@ /* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */ -#include +#include #include #include #include diff --git a/drivers/marvell/iob.c b/drivers/marvell/iob.c index acc4941f5..e88bc1673 100644 --- a/drivers/marvell/iob.c +++ b/drivers/marvell/iob.c @@ -7,7 +7,7 @@ /* IOW unit device driver for Marvell CP110 and CP115 SoCs */ -#include +#include #include #include #include diff --git a/include/plat/marvell/a8k/common/a8k_common.h b/include/plat/marvell/a8k/common/armada_common.h similarity index 100% rename from include/plat/marvell/a8k/common/a8k_common.h rename to include/plat/marvell/a8k/common/armada_common.h diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c index 917198670..26b67eb6d 100644 --- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c @@ -5,7 +5,7 @@ * https://spdx.org/licenses */ -#include +#include /* * If bootrom is currently at BLE there's no need to include the memory diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c index ec4124c13..f8a1c40be 100644 --- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c @@ -5,7 +5,7 @@ * https://spdx.org/licenses */ -#include +#include /* * If bootrom is currently at BLE there's no need to include the memory diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 43beffabf..4948c9a33 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -5,7 +5,8 @@ * https://spdx.org/licenses */ -#include +#include + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c index 079bd8fef..384d0f54b 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -5,9 +5,10 @@ * https://spdx.org/licenses */ -#include +#include #include #include + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index 21541855b..973c56dc8 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -5,7 +5,7 @@ * https://spdx.org/licenses */ -#include +#include #include #include #include diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c index 6c85fcc37..e6ffeeab1 100644 --- a/plat/marvell/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/a8k/common/plat_bl31_setup.c @@ -5,7 +5,7 @@ * https://spdx.org/licenses */ -#include +#include #include #include #include diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 0cd62cbdb..d2607dafc 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -5,8 +5,8 @@ * https://spdx.org/licenses */ -#include #include +#include #include #include #include diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index c716ee0f7..ec4b55b39 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -5,7 +5,7 @@ * https://spdx.org/licenses */ -#include +#include #include #include #include From 3a9f8eecd7eb4526ec4b6b5d7231038f9e32a3a5 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Wed, 13 Jun 2018 15:27:10 +0200 Subject: [PATCH 03/17] drivers: marvell: mc_trustzone: add driver for mc trustzone Add simple driver which allows to configure the memory controller trust zones. It is responsible for opening mc trustzone window, with appropriate base address, size and attributes. Example of usage in upcoming commits. Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Kostya Porotchkin --- drivers/marvell/mc_trustzone/mc_trustzone.c | 71 +++++++++++++++++++++ drivers/marvell/mc_trustzone/mc_trustzone.h | 27 ++++++++ 2 files changed, 98 insertions(+) create mode 100644 drivers/marvell/mc_trustzone/mc_trustzone.c create mode 100644 drivers/marvell/mc_trustzone/mc_trustzone.h diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.c b/drivers/marvell/mc_trustzone/mc_trustzone.c new file mode 100644 index 000000000..0db3b8d09 --- /dev/null +++ b/drivers/marvell/mc_trustzone/mc_trustzone.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include "mc_trustzone.h" + +#define TZ_SIZE(x) ((x) >> 13) + +static int fls(int x) +{ + if (!x) + return 0; + + return 32 - __builtin_clz(x); +} + +/* To not duplicate types, the addr_map_win is used, but the "target" + * filed is referring to attributes instead of "target". + */ +void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id) +{ + int tz_size; + uint32_t val, base = win->base_addr; + + if ((win_id < 0) || (win_id > MVEBU_TZ_MAX_WINS)) { + ERROR("Enabling wrong MC TrustZone window %d!\n", win_id); + return; + } + + /* map the window size to trustzone register convention */ + tz_size = fls(TZ_SIZE(win->win_size)); + + VERBOSE("%s: window size = 0x%llx maps to tz_size %d\n", + __func__, win->win_size, tz_size); + if (tz_size < 0 || tz_size > 31) { + ERROR("Using not allowed size for MC TrustZone window %d!\n", + win_id); + return; + } + + if (base & 0xfff) { + base = base & ~0xfff; + WARN("Attempt to open MC TZ win. at 0x%llx, truncate to 0x%x\n", + win->base_addr, base); + } + + val = base | (tz_size << 7) | win->target_id | TZ_VALID; + + VERBOSE("%s: base 0x%x, tz_size moved 0x%x, attr 0x%x, val 0x%x\n", + __func__, base, (tz_size << 7), win->target_id, val); + + mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val); + + VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, + MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), + mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id))); + + mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), + (win->base_addr >> 32)); + + VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, + MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), + mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id))); +} diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.h b/drivers/marvell/mc_trustzone/mc_trustzone.h new file mode 100644 index 000000000..8a0692331 --- /dev/null +++ b/drivers/marvell/mc_trustzone/mc_trustzone.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef _MC_TRUSTZONE_H +#define _MC_TRUSTZONE_H + +#include + +#define MVEBU_TZ_MAX_WINS 16 + +#define TZ_VALID (1 << 0) +#define TZ_PERM(x) ((x) << 1) +#define TZ_RZ_ENABLE (1 << 3) + +/* tz attr definitions */ +#define TZ_PERM_RW (TZ_PERM(0)) +#define TZ_PERM_RO (TZ_PERM(1)) +#define TZ_PERM_WO (TZ_PERM(2)) +#define TZ_PERM_ABORT (TZ_PERM(3)) + +void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id); + +#endif /* _MC_TRUSTZONE_H */ From de5cba28c43c2be7968c1ad15f15aae2fc823e51 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Wed, 13 Jun 2018 16:00:48 +0200 Subject: [PATCH 04/17] a8k: use the memory controller feature to protect the RT service region Define the RT service space as secure with use of memory controller trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS, won't be able to access RT services (e.g. accidentally overwrite it, which will at best result in RT services unavailability). Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Kostya Porotchkin --- plat/marvell/a8k/common/a8k_common.mk | 3 ++- plat/marvell/a8k/common/plat_bl31_setup.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index 3bcce96b2..5956737db 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -76,7 +76,8 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \ $(MARVELL_DRV_BASE)/amb_adec.c \ $(MARVELL_DRV_BASE)/ccu.c \ $(MARVELL_DRV_BASE)/cache_llc.c \ - $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c + $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \ + $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c index e6ffeeab1..6dfbcbb20 100644 --- a/plat/marvell/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/a8k/common/plat_bl31_setup.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -75,6 +76,24 @@ _Bool is_pm_fw_running(void) return pm_fw_running; } +/* For TrusTzone we treat the "target" field of addr_map_win + * struct as attribute + */ +static const struct addr_map_win tz_map[] = { + {PLAT_MARVELL_ATF_BASE, 0x200000, TZ_PERM_ABORT} +}; + +/* Configure MC TrustZone regions */ +static void marvell_bl31_security_setup(void) +{ + int tz_nr, win_id; + + tz_nr = ARRAY_SIZE(tz_map); + + for (win_id = 0; win_id < tz_nr; win_id++) + tz_enable_win(MVEBU_AP0, tz_map, win_id); +} + /* This function overruns the same function in marvell_bl31_setup.c */ void bl31_plat_arch_setup(void) { @@ -116,4 +135,6 @@ void bl31_plat_arch_setup(void) /* Configure GPIO */ marvell_gpio_config(); + + marvell_bl31_security_setup(); } From 5b0a152a57f94166a878274f9dcad04cc5aa4647 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 17 Jul 2018 15:20:08 +0200 Subject: [PATCH 05/17] plat: marvell: a70x0: reconfigure CP0 PCIE2 windows In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94 Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin --- plat/marvell/a8k/a70x0/board/marvell_plat_config.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c index 26b67eb6d..d126f5567 100644 --- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c @@ -76,6 +76,8 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f7000000, 0x1000000, PEX1_TID}, /* PEX2_X1 window */ {0x00000000f8000000, 0x1000000, PEX2_TID}, + {0x00000000c0000000, 0x30000000, PEX2_TID}, + {0x0000000800000000, 0x100000000, PEX2_TID}, /* PEX0_X4 window */ {0x00000000f6000000, 0x1000000, PEX0_TID}, /* SPI1_CS0 (RUNIT) window */ @@ -101,6 +103,8 @@ struct addr_map_win ccu_memory_map[] = { /* IO window */ {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else {0x00000000f2000000, 0xe000000, IO_0_TID}, + {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ + {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ #endif }; From b0f2361a1a060b7b75181ffe3b99169f35312042 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 17 Jul 2018 15:26:21 +0200 Subject: [PATCH 06/17] plat: marvell: a80x0: reconfigure CP0 PCIE0 windows In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: Ia8177194e542078772f90941eced81b231c16887 Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin --- plat/marvell/a8k/a80x0/board/marvell_plat_config.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 4948c9a33..7901dd225 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -86,7 +86,9 @@ struct addr_map_win iob_memory_map_cp0[] = { /* PEX2_X1 window */ {0x00000000f8000000, 0x1000000, PEX2_TID}, /* PEX0_X4 window */ - {0x00000000f6000000, 0x1000000, PEX0_TID} + {0x00000000f6000000, 0x1000000, PEX0_TID}, + {0x00000000c0000000, 0x30000000, PEX0_TID}, + {0x0000000800000000, 0x100000000, PEX0_TID}, }; struct addr_map_win iob_memory_map_cp1[] = { @@ -130,6 +132,8 @@ struct addr_map_win ccu_memory_map[] = { {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ + {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ + {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ #endif }; From f858e989c607fca1d76207f4c918e82dac1c7221 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 12 Jul 2018 07:40:34 +0200 Subject: [PATCH 07/17] mvebu: cp110: align all comphy_index arguments type The biggest comphy index can be equal to 6 so there is no need to use uint64_t for storing it. Change-Id: I14c2b68e51678a560815963c72aed0c37068f926 Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Igal Liberman Reviewed-by: Kostya Porotchkin --- drivers/marvell/comphy/phy-comphy-cp110.c | 6 +++--- drivers/marvell/comphy/phy-comphy-cp110.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 8b78280b5..326d5a85d 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -2201,7 +2201,7 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, return 0; } -int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index, +int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, uint64_t comphy_mode) { int mode = COMPHY_GET_MODE(comphy_mode); @@ -2247,7 +2247,7 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index, err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index); break; default: - ERROR("comphy%lld: unsupported comphy mode\n", comphy_index); + ERROR("comphy%d: unsupported comphy mode\n", comphy_index); err = -EINVAL; break; } @@ -2257,7 +2257,7 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint64_t comphy_index, return err; } -int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint64_t comphy_index) +int mvebu_cp110_comphy_power_off(uint64_t comphy_base, uint8_t comphy_index) { uintptr_t sd_ip_addr, comphy_ip_addr; uint32_t mask, data; diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h index ada6aecae..2461e5ca9 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.h +++ b/drivers/marvell/comphy/phy-comphy-cp110.h @@ -8,11 +8,11 @@ /* Marvell CP110 SoC COMPHY unit driver */ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, - uint64_t comphy_index); + uint8_t comphy_index); int mvebu_cp110_comphy_power_off(uint64_t comphy_base, - uint64_t comphy_index); + uint8_t comphy_index); int mvebu_cp110_comphy_power_on(uint64_t comphy_base, - uint64_t comphy_index, uint64_t comphy_mode); + uint8_t comphy_index, uint64_t comphy_mode); int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base, uint8_t comphy_index); int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index, From 3c0024cc2ceb6137e2bd01c6b9bb7274352cfedc Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Mon, 16 Jul 2018 12:18:03 +0200 Subject: [PATCH 08/17] mvebu: cp110: fix spelling in register definition Use PF instead of PP post-fix, since it is referring to "Phase Final" (only G3 related register had correct spelling for relevant bit). Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Igal Liberman Reviewed-by: Kostya Porotchkin --- drivers/marvell/comphy/comphy-cp110.h | 12 ++++++------ drivers/marvell/comphy/phy-comphy-cp110.c | 24 +++++++++++------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h index 925abb5e5..6afa2c227 100644 --- a/drivers/marvell/comphy/comphy-cp110.h +++ b/drivers/marvell/comphy/comphy-cp110.h @@ -217,9 +217,9 @@ #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ - (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3 +#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) @@ -251,9 +251,9 @@ #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ - (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3 +#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 326d5a85d..19bd182fa 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -481,8 +481,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* G1 settings */ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; @@ -506,8 +506,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* G2 settings */ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; @@ -1000,13 +1000,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, if (speed == COMPHY_SPEED_5_15625G) { mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; } else { mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; @@ -1504,8 +1504,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Genration 2 setting 1*/ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; - mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); @@ -1741,8 +1741,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, /* 0xE-G1_Setting_1 */ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); From 155d01ff1eea98fbec128688eedbefc8a6b798af Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Thu, 16 Nov 2017 18:19:02 +0100 Subject: [PATCH 09/17] marvell: pm: do not panic by default in cpu_standby Current default behavior of cpu_standby callback is problematic during the SBSA test, which is unable to run due to EL3 panic. Make it dependent on the PM firmware running. Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8 Signed-off-by: Marcin Wojtas Reviewed-by: Grzegorz Jaszczyk Reviewed-by: Kostya Porotchkin --- plat/marvell/a8k/common/plat_pm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index ec4b55b39..0c74b2fe5 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -379,8 +379,10 @@ static int a8k_validate_power_state(unsigned int power_state, */ static void a8k_cpu_standby(plat_local_state_t cpu_state) { - ERROR("%s: needs to be implemented\n", __func__); - panic(); + if (!is_pm_fw_running()) { + ERROR("%s: needs to be implemented\n", __func__); + panic(); + } } /***************************************************************************** From 4acd900df6275cd724266157e04e2b75d82cf24a Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Wed, 21 Mar 2018 09:55:47 +0100 Subject: [PATCH 10/17] gicv2: enable configuring IRQ trigger type This patch introduces new helper routines that allow configuring the individual IRQs to be edge/level-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the non-secure GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin --- drivers/arm/gic/v2/gicv2_main.c | 9 +++++++++ include/drivers/arm/gicv2.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 7cf6c76e3..a355659d2 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -593,3 +593,12 @@ unsigned int gicv2_set_pmr(unsigned int mask) return old_mask; } + +/******************************************************************************* + * This function updates single interrupt configuration to be level/edge + * triggered + ******************************************************************************/ +void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) +{ + gicd_set_icfgr(driver_data->gicd_base, id, cfg); +} diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index 925d1c25c..3472c37d7 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -191,6 +191,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num); void gicv2_set_interrupt_pending(unsigned int id); void gicv2_clear_interrupt_pending(unsigned int id); unsigned int gicv2_set_pmr(unsigned int mask); +void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg); #endif /* __ASSEMBLY__ */ #endif /* __GICV2_H__ */ From 349df242edb80143a9b8a944732d9fc8fcead248 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Mon, 30 Jul 2018 10:18:45 +0200 Subject: [PATCH 11/17] marvell: drivers: correct RTC init sequence It turned out that resetting the RTC time register is not necessary during initial configuration. Safely remove it from the sequence. Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee Signed-off-by: Marcin Wojtas Reviewed-by: Nadav Haklai Reviewed-by: Kostya Porotchkin --- drivers/marvell/mochi/cp110_setup.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index c4cb307f9..654bb62b2 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -341,10 +341,6 @@ static void cp110_rtc_init(uintptr_t base) mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); mdelay(500); - /* Reset Time register */ - mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); - udelay(62); - /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, (MVEBU_RTC_STATUS_ALARM1_MASK | @@ -361,10 +357,6 @@ static void cp110_rtc_init(uintptr_t base) mmio_write_32(base + MVEBU_RTC_CCR_REG, MVEBU_RTC_NOMINAL_TIMING); - /* Reset Time register */ - mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); - udelay(10); - /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, (MVEBU_RTC_STATUS_ALARM1_MASK | From fd1718a2ff27ba44b1662673580828da615f6402 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Wed, 21 Mar 2018 09:59:59 +0100 Subject: [PATCH 12/17] plat: a8k: enable PMU overflow interrupt handler This patch enables handling PMU overflow IRQ by GIC SPI's directly in EL3. Also implement additional SMC routine, which can disable the solution on demand in runtime. Since it is possible to configure PMU interrupt trigger type in the MADT ACPI table, it is enough to set it only once in EL3 during initialization. Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a Signed-off-by: Marcin Wojtas Reviewed-by: Kostya Porotchkin --- include/plat/marvell/a8k/common/marvell_def.h | 1 + .../plat/marvell/a8k/common/plat_marvell.h | 8 ++ .../marvell/a8k/common/include/platform_def.h | 4 + plat/marvell/common/marvell_gicv2.c | 87 +++++++++++++++++++ plat/marvell/common/mrvl_sip_svc.c | 11 +++ 5 files changed, 111 insertions(+) diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/a8k/common/marvell_def.h index 7dacf820a..9429753ce 100644 --- a/include/plat/marvell/a8k/common/marvell_def.h +++ b/include/plat/marvell/a8k/common/marvell_def.h @@ -63,6 +63,7 @@ #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ MARVELL_DRAM_SIZE - 1) +#define MARVELL_IRQ_PIC0 28 #define MARVELL_IRQ_SEC_PHY_TIMER 29 #define MARVELL_IRQ_SEC_SGI_0 8 diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h index 81cbf3871..9ca68d3bc 100644 --- a/include/plat/marvell/a8k/common/plat_marvell.h +++ b/include/plat/marvell/a8k/common/plat_marvell.h @@ -93,6 +93,14 @@ int marvell_io_is_toc_valid(void); void marvell_psci_arch_init(int ap_idx); void plat_marvell_system_reset(void); +/* + * Miscellaneous platform SMC routines + */ +#ifdef MVEBU_PMU_IRQ_WA +void mvebu_pmu_interrupt_enable(void); +void mvebu_pmu_interrupt_disable(void); +#endif + /* * Optional functions required in Marvell standard platforms */ diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index f7bd23fa2..06d4fa9cf 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -134,6 +134,8 @@ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MARVELL_IRQ_PIC0, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL) #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ @@ -199,4 +201,6 @@ #define BL32_BASE TRUSTED_DRAM_BASE +#define MVEBU_PMU_IRQ_WA + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/marvell/common/marvell_gicv2.c b/plat/marvell/common/marvell_gicv2.c index ba8e40961..19e1ec0f5 100644 --- a/plat/marvell/common/marvell_gicv2.c +++ b/plat/marvell/common/marvell_gicv2.c @@ -5,7 +5,11 @@ * https://spdx.org/licenses */ +#include +#include #include +#include +#include #include #include #include @@ -17,6 +21,21 @@ #pragma weak plat_marvell_gic_driver_init #pragma weak plat_marvell_gic_init +#define A7K8K_PIC_CAUSE_REG 0xf03f0100 +#define A7K8K_PIC0_MASK_REG 0xf03f0108 + +#define A7K8K_PIC_PMUOF_IRQ_MASK (1 << 17) + +#define A7K8K_PIC_MAX_IRQS 32 +#define A7K8K_PIC_MAX_IRQ_MASK ((1UL << A7K8K_PIC_MAX_IRQS) - 1) + +#define A7K8K_ODMIN_SET_REG 0xf0300040 +#define A7K8K_ODMI_PMU_IRQ(idx) ((2 + idx) << 12) + +#define A7K8K_ODMI_PMU_GIC_IRQ(idx) (130 + idx) + +static DEFINE_BAKERY_LOCK(a7k8k_irq_lock); + /* * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. @@ -50,6 +69,74 @@ void plat_marvell_gic_driver_init(void) gicv2_driver_init(&marvell_gic_data); } +static uint64_t a7k8k_pmu_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + unsigned int idx = plat_my_core_pos(); + uint32_t irq; + + bakery_lock_get(&a7k8k_irq_lock); + + /* Acknowledge IRQ */ + irq = plat_ic_acknowledge_interrupt(); + + plat_ic_end_of_interrupt(irq); + + if (irq != MARVELL_IRQ_PIC0) { + bakery_lock_release(&a7k8k_irq_lock); + return 0; + } + + /* Acknowledge PMU overflow IRQ in PIC0 */ + mmio_setbits_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_PMUOF_IRQ_MASK); + + /* Trigger ODMI Frame IRQ */ + mmio_write_32(A7K8K_ODMIN_SET_REG, A7K8K_ODMI_PMU_IRQ(idx)); + + bakery_lock_release(&a7k8k_irq_lock); + + return 0; +} + +void mvebu_pmu_interrupt_enable(void) +{ + unsigned int idx; + uint32_t flags; + int32_t rc; + + /* Reset PIC */ + mmio_write_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_MAX_IRQ_MASK); + /* Unmask PMU overflow IRQ in PIC0 */ + mmio_clrbits_32(A7K8K_PIC0_MASK_REG, A7K8K_PIC_PMUOF_IRQ_MASK); + + /* Configure ODMI Frame IRQs as edge triggered */ + for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) + gicv2_interrupt_set_cfg(A7K8K_ODMI_PMU_GIC_IRQ(idx), + GIC_INTR_CFG_EDGE); + + /* + * Register IRQ handler as INTR_TYPE_S_EL1 as its the only valid type + * for GICv2 in ARM-TF. + */ + flags = 0U; + set_interrupt_rm_flag((flags), (NON_SECURE)); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + a7k8k_pmu_interrupt_handler, + flags); + if (rc != 0) + panic(); +} + +void mvebu_pmu_interrupt_disable(void) +{ + /* Reset PIC */ + mmio_write_32(A7K8K_PIC_CAUSE_REG, A7K8K_PIC_MAX_IRQ_MASK); + /* Mask PMU overflow IRQ in PIC0 */ + mmio_setbits_32(A7K8K_PIC0_MASK_REG, A7K8K_PIC_PMUOF_IRQ_MASK); +} + void plat_marvell_gic_init(void) { gicv2_distif_init(); diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c index ec293afa3..a0ca50d0a 100644 --- a/plat/marvell/common/mrvl_sip_svc.c +++ b/plat/marvell/common/mrvl_sip_svc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "comphy/phy-comphy-cp110.h" @@ -30,6 +31,8 @@ /* Miscellaneous FID's' */ #define MV_SIP_DRAM_SIZE 0x82000010 #define MV_SIP_LLC_ENABLE 0x82000011 +#define MV_SIP_PMU_IRQ_ENABLE 0x82000012 +#define MV_SIP_PMU_IRQ_DISABLE 0x82000013 #define MAX_LANE_NR 6 #define MVEBU_COMPHY_OFFSET 0x441000 @@ -109,6 +112,14 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, llc_runtime_enable(i); SMC_RET1(handle, 0); +#ifdef MVEBU_PMU_IRQ_WA + case MV_SIP_PMU_IRQ_ENABLE: + mvebu_pmu_interrupt_enable(); + SMC_RET1(handle, 0); + case MV_SIP_PMU_IRQ_DISABLE: + mvebu_pmu_interrupt_disable(); + SMC_RET1(handle, 0); +#endif default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); From dd47809e9ea75188060bf8b294efa8578d255c63 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 14 Aug 2018 12:26:45 +0300 Subject: [PATCH 13/17] fix: marvell: Check the required libraries before building doimage Some customers are missing host libraries required for doimage builds. This patch requests for the library installation check for every doimage build and suggest the required installation steps in case of missing headers. Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e Signed-off-by: Konstantin Porotchkin Reviewed-by: Igal Liberman --- plat/marvell/marvell.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk index 217ad46f0..2a2da3b93 100644 --- a/plat/marvell/marvell.mk +++ b/plat/marvell/marvell.mk @@ -48,6 +48,7 @@ mrvl_clean: ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean ${DOIMAGETOOL}: mrvl_clean + @$(DOIMAGE_LIBS_CHECK) ${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH} WTMI_IMG=$(WTMI_IMG) From 6384f0acf0772ce1d0505b9c4b3671e53fb91240 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 14 Aug 2018 15:25:07 +0300 Subject: [PATCH 14/17] tools: doimage: Add secure image key file examples Add example keys for building trusted flash images using doimage tools. Similar files can be generated using openssl or mbedtls. Marvell platform make files are using trusted boot configurations from this example etst vector. Change-Id: I38a2e295171bee4c14005ce6f020b352c683496e Signed-off-by: Konstantin Porotchkin --- tools/doimage/secure/aes_key.txt | 1 + tools/doimage/secure/csk_priv_pem0.key | 27 ++++++++++++++++++++++++ tools/doimage/secure/csk_priv_pem1.key | 27 ++++++++++++++++++++++++ tools/doimage/secure/csk_priv_pem2.key | 27 ++++++++++++++++++++++++ tools/doimage/secure/csk_priv_pem3.key | 27 ++++++++++++++++++++++++ tools/doimage/secure/kak_priv_pem.key | 27 ++++++++++++++++++++++++ tools/doimage/secure/sec_img_7K.cfg | 29 ++++++++++++++++++++++++++ tools/doimage/secure/sec_img_8K.cfg | 29 ++++++++++++++++++++++++++ 8 files changed, 194 insertions(+) create mode 100644 tools/doimage/secure/aes_key.txt create mode 100644 tools/doimage/secure/csk_priv_pem0.key create mode 100644 tools/doimage/secure/csk_priv_pem1.key create mode 100644 tools/doimage/secure/csk_priv_pem2.key create mode 100644 tools/doimage/secure/csk_priv_pem3.key create mode 100644 tools/doimage/secure/kak_priv_pem.key create mode 100644 tools/doimage/secure/sec_img_7K.cfg create mode 100644 tools/doimage/secure/sec_img_8K.cfg diff --git a/tools/doimage/secure/aes_key.txt b/tools/doimage/secure/aes_key.txt new file mode 100644 index 000000000..3e8a88836 --- /dev/null +++ b/tools/doimage/secure/aes_key.txt @@ -0,0 +1 @@ +ABCDEF1234567890ABCDEF1234567890ABCDEF1234567890ABCDEF1234567890 diff --git a/tools/doimage/secure/csk_priv_pem0.key b/tools/doimage/secure/csk_priv_pem0.key new file mode 100644 index 000000000..0840c2a01 --- /dev/null +++ b/tools/doimage/secure/csk_priv_pem0.key @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEogIBAAKCAQEAm6jN6o2zQmtyUlvfkfDbSjPJ7Vlpp/KgK/eznoVBBsDIZakX +cIgf8TSLpNVkc+ZE0f/n8X7mEZIyjuSBObLOm9vbkoZcR7DlKUL7RNNOUCv55Ozl +hQwrzpH/uIyIJTvmek29G5wroi0wGbPoxzhelIRTjVCibleBWhYCmZQ6SIRmTY8L +JT8VkX8I/Mhu62DjvxF3BnV6pXuh/FdgDN7MbldzM8Y+GOxVGi5Kcm5WHY7eyMxl +4Y0Yko31Xv7T1PcXahVBIciT+11w+fLc4wQuCJ6GUf9JbzQ0ZllY/FdRG0AhuRMH +zN0jAc/sKrIFoAErED6qlcoQg0vl7gmWN5x+2wIDAQABAoIBACtnPFOkw1FH6I6y +c3qcMGlWW33FKsLb0nGwFfOjsGgTpU1Dgver3UxCnJWPsvzmPlZYBvK9saVAoLxb +VvUhuJ6ZBXar5FtRJfUFak7cpL+SI5IDxFP++tAUwbtR5DyNoUyFFK/4Mep8sybX +lZbHTwgWhb2nuEMQP09BR+RPAplpcitkIoPkhmbGfbt9Hsd25I3bb5Z9R4S/2Rcf +7tmaxndQamij7/pUI7xtd8L6cMESJGIWrgEt/MaT2z8nNPE3EDctDSlH9yKqA2O7 +/LTfrxNDnw5gGRtOgahloThKljVM6pQa4mi91FufD67pHwnKn8urNbt8/3AWg6uU +x4FzZdECgYEA0k2UYzBM+dU6T1bZZ176YI0cZrP1tbf/JwnZGHicQYS7lPLAqgfO +u5oRQzuDimOXaV4xCPBO2nadd6aBxbZTXaglR7GG2uCHX6w2DnOr8/d66YTErTVV +u7/Bf8gMKT9mM4rWPrOEXfXfF0fvcpkBQ+QDynIB37tx/mj2lXRkLx0CgYEAvXuX +Dbe2QgSK0ajrcH7YJyx3RVx9RonOqL4yjCVCELmaDQd307Ef3j+gkd59XIewm+HA +mPyeWEUd8EzH+UvjckfKFuF2I4lEUUWtVZTa7me7mvsFqeEOu5KusD4+Hs+B9Kqd +3Evqcpj2lcMBI519Hvr9BTKfDBcH1EUos6A9rFcCgYAxsyPeTQvj/wBIv72hMFD7 +gF2159GpoFIsZ6dmoRpMYZHzIWtmw3GX5FEwEmCD1AV0YU41TpVUC7QrEq6Yiv4o +pBQrXUkBcQ6NDaW4xJ1eip4Bkd7pEDGyrR6NlDlLhjAg/i6joskla3XNirKL4pzp +7nj23vqSZToLZcLgjyEeAQKBgD5EvDo80j9VwMzvpxecB6qv+S4pG94vcWOQxYm6 +wMBATjjT6HP/9EoUPM9S/32F9er0QFfGRL8bT6Blix4I62Dl6KqmQy2gcXwH2tOS +DHRmUIe40H6oQDAyHwg6HC4B4WInI6N+qzgnvnku0VQD8FdbAgVQQmY1t1PxulN1 +aG8XAoGAPWAr4i8KkVAx4wLlMF8E/ecKcsX1J0+UuKket7Dvk7xJfwtkSLPeV8Bp +HuoHXMM3KYoZ93Hlto5rAT1VQhYuj7heU10v+9UtYTFHgaitptYmxovoCKKiZICl +48aPUI377e5jQ6RhhGYy8ltKsJ80K1T9DIkThJPSS+9NAI+jrmg= +-----END RSA PRIVATE KEY----- diff --git a/tools/doimage/secure/csk_priv_pem1.key b/tools/doimage/secure/csk_priv_pem1.key new file mode 100644 index 000000000..91d1aeb1d --- /dev/null +++ b/tools/doimage/secure/csk_priv_pem1.key @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEogIBAAKCAQEAgwHXB0AaIhT15Z9lHpQ2YT1W8i4oMvvRiLGQCrba5l7BJ03E +ct0x3zagNKZEnpNndT4EAy98ihkhwVlUhxZCparJ2L3JsTs5RgV0wyQkQzwMLM8g +QI5EMmJCgFAVRHmVICOsisGGfNVUHjGdGwPOipyQCsX2MAm3E139VpB7NYj+Q4IR +4kvcb+59LZxKuRJTFKRDIqMGJu98P/ga70+YLXPCBPKSfnZnUppuaI86jF1E6xt8 +o7YtfEPCHDd2LXxKPZ670OapVqwo0t7ZSzEG63NkLp56FXc1OpfC69C8VPiZ8JqW +wxvS/vL8MMCxsBnjSuqnmOAbcNR2GFtUwJOGwwIDAQABAoIBAFcfoiDwQHDp/531 +ownzBzcj0+67Q4Ckd3SwoVp+wJTz7wB0d3DsKX6IlYJuELRk0yjlVUXJDsnIbOpo +vg4Yf7otGo9JqBh1imFGv6AHKRaNmIs0M/66nh/juNYcbAhd0w7MqrKcgRQDyy1J +UXHl1jXYaPLBNDg+PcJjf1dSPp4axzmW2Pk2rXnJCsPcZXL/0YmEvqhfOze0GdjR +hOkbbr6MPPVM66tA00xSwg9XEYJvHtwH6oB0rnANM8ieNK1mtcWkTU5di17CCrjS +ohIhXQrdVpxt549EJoUqEFSgo8OOMm2npDbFrjlukb5euakvMacwoT1te79blSKf +hrTvjgECgYEA0VqoFL0Vqe1qleikYDJ7S5xcv1oruEV31TeuBhDuf0c4PADCnBrV +/RnCEYuXs6wCk60chHg5s0jxg+nGbiY6jRTHkJLRU3ZhDtrtfidEZ78GRzFF3shl +Uzt7dHkKK1ZdiMH4sWzyRLom91TKWMrNKC1AD7v4/zjEXy6phall3ZcCgYEAoDJa +0dIKvVCS6dM2E2kMqi/45mJqsJzFvYL1s4mbma/BAC47bBju/YEse90x+iIi3Gg/ +NoXmNfGPrtgdl+/J/Y6Pohxf/e7gGN71tYVETzgc2Jv09wqmzmTjCmo3wyepyWf+ +pIAE39kdhwnqXVw5xwOG1N3xrQ9TomOO+1QiXbUCgYAF84TJqiJehUA9aLKbhXPZ +z2UXj3GkuFzSs9V/mKWe+qBPnFnr5BtnKX9JzmUOl3ovRoGEBoLlZNJwxIl+ghmx +/wA5TOMkcz4JFRIhPu6D4HtGNNFepuWyewNkaThvyPG5vIHcUVOFvqDy8PcblRBF +7xteFyLZ5nw2lHX/NbSOmwKBgFxLZqPIPcPArkPlGhyow1Ex/lbNkOZcDFkZIHHl +8C3lYm62NCodW2PWjkh2shqInEkcDn9dObsOh1eWz8X/swJQplQhwPROMfJiUnHY +a/iwPX5WrBXAn0X+Pgh8FdBsA5g0QDOKRkSplCd/APX08pzEXWQ60siAMhE3BuOq +H3qZAoGAVnzFidlXuyn+fbNaNVepK9hbuoxHHbzYYWSkpi+73EchN8kXktC+AdEf +owr9TPILbwWWJyisa3wW4xdbMifCgVLTedWZpZ09BENVqC+7g7ksX0pNMGYuFLOh +Td7mFAgmclxG5UiKexajOLjjdnAsJyrDaNKhHn8NQNN6L93N0sE= +-----END RSA PRIVATE KEY----- diff --git a/tools/doimage/secure/csk_priv_pem2.key b/tools/doimage/secure/csk_priv_pem2.key new file mode 100644 index 000000000..ea47ac5f8 --- /dev/null +++ b/tools/doimage/secure/csk_priv_pem2.key @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEogIBAAKCAQEAjxTSTh57/5njUpE200+Qb3ySAn8lKeufgaa0K2Xc6Ri7lDZR +ZJ2BPuQZV4lYGqgWUf0IOzNf2WnE2lPfVnLMx08h7NhBqJ83yJVajpr+itnOmW+r +M7h76TFyuna1xz2kw1uhgI5Y4FRnJ4Cg4AexCSyViXSzEN/7LQwxa5z5WGDiNX5N +3/tgjGu+dzSMOiIQhXwIcK/XaiQNm3WHqqnAhPb5Q9IBuuqBfpZoFfH4XmbFWrC8 +neSMMMxX5Ti9pKhLd1EsiaP0aUNQlF8gNWuC/tNaf+OCtwVelVa3sGSRjRFe06VQ +sAE9oyXKri11yD5Dwp1xXivbpOrf7xjUe5gILwIDAQABAoIBABTr94CCxqDucKYP +I9QsSzNyJKuGyfliQdWkea3q3C2ddzhJ5QbwXQjEM8xwAdkMAQ+GD2EQtxBEfgtq +vjqW2MjAEnbefGNavL5w0GgP0+6bwLEA+ii67iuAFoWbfCMhKWmDiY8RwX8z+E13 +ao63sTRlN4x86v4pskG5CbTxpCg+8m7KklLns4SwRGf5gGQcgKRtNSR5nE4g2UNl +dghbDdNlvUncm4zxUcTh0kquhF5Tef5w+6L7W8Hv9Pky3b1c2OK1BMhJlxYrtt69 +/zhIJs89CLx5ACfam+DT/xs0uUiuRQq/e1CCQLCnUO02JqpeN/schtDCd0ZWhbtB +nT7fwTECgYEAx+COhys+7AZI0U+PeuTkI86GUsWHoBislXThxbxyGvMFjgyADZD+ +q/XEGAcxd4eTA1fr0Q9cLuuHZubjGQ7+OIXMZ6arXUsrmMrjRu3kHO+y6K6r4s8j +5bxN/iQ0bymUtJRfJSLI172plszusiPWhCL5+yhYlNoh4mNZJuJnzXkCgYEAt0Gz +07P19YPsxk5ow7ZnSNOMOkkEPP0SuHHWekMIK9KMjiRUSygOAk07zTL7MUoFn9Gy +Prfi0ybFArNhIa4Xio3Fbjfig7rGgaApK4Y3d9A/CGPv/Nj7C2OTepqlEzRLmU9e +Xw5yhbccCydXLyAYFAET2XHsmbewpvHyeYUSoOcCgYBRMJEUrOdhPmhDxZqVo/Zb +6R887gnaaUtpZlHzXUnIUqEWA1PcruIT/b/KttlMIWEBQayDfkbGtFuK3AyxeBqh +4Q+XpucC/W7XIMrTW/yGGIPG6nTdq6B8SFIyAojeArjp5T8Eua11nRAPNm1bJR2V +DRQYBlp9FGIhMJPdLKhXmQKBgGeywSyR0COfBHPu2K+u3uFB/D7bJI/ScS54FHLY +zZ3mpeylOCHTR6IbzDRAng31Ihue0KtW6P6tGJx/nv4tAltAADFvZDlAjqW5WLKt +X2PoLlL0IlBFBEIclc6yBalJVWIqnG9TwJBT3oWdPGOJWLaxKWdJZSZS4J6HmLsV +B0aPAoGAduLsOt8C5z48jPqmJxyPwsmT0Q424FccPMcvGOJ13yxq3xNsfAsbmg9l +L2i/ktE0wCMA+Pm7cuFgxwD7xTr67POZgt9022KsOSonjPsIn24UQeP46vAX/Qtx +Qf3sfvzf57vNy2Hybe38T8RsVOZla+v/QctfSfmb8Y95XL/SZzA= +-----END RSA PRIVATE KEY----- diff --git a/tools/doimage/secure/csk_priv_pem3.key b/tools/doimage/secure/csk_priv_pem3.key new file mode 100644 index 000000000..e40a86422 --- /dev/null +++ b/tools/doimage/secure/csk_priv_pem3.key @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEowIBAAKCAQEAlA/T/5IMTPTu+k5PeesB2oeP80Y6nq0ls8vXLul0TVEJoJ+O +InbPYNqYPu4dbQQg/u8qp8BeXm2ujtJbBTcdn0jKIiDTKYEnlsGfUt9GHnuuzvFh +rORSKuAolUqvo/zcSCo1uykaFvSuyTovSPlwllzSixD9XBbHfn3kXneiIUa45vsJ +AyjTn2qCJt0WgvX42NTxH6Q/OWLeOuKTyRHf25eabucIv77KYy0mlEPq5jjiV5AJ +gl5F1h5G8n07JCIWjkZ2QV4wr+Hv9uGNaSb0WGppBp4CbdQa0eUI75cKzz4WXqds +HZaYiX/a8YC+EUfvqDD02vKREIKFL/1zL53P/wIDAQABAoIBAGzBj5w7oBNrGpr7 +qL9KEyt8xg0Q+gAR+Q6vXRlVXBtquiKk8Jd6I+vlxUz8RNsN3FrGPNPJpse/0yeP +dlJHYNfedLNK3zCucPD4uln6LRw5B3d0sKV5dK2Px9+ZY5iWJQxRDPS0RTi1dCnV +NmRo7P1Vo0WJLkFVbiYIvRVy1MGRfF9ejN41G6U4MoBAQ9WqLp+JasUMTspZI49a +z8tOiJPT94MHBwbKnz8Mcq8sy02LR7U5h82+0T7JoRVix/OXiOoiQExNjZ9yGar0 +wBnl0SL1UW5UUaYzbyNH0mlMXLD+qowbDZM2pBWPfqXK+CMOsL6STIwnns7lY+ZJ +ILbaVmECgYEA2kQXE1PZ25A87a81wCEld402WJ2KegrZC719EWv+xeoS72Ji8uv7 +V0PxVGJQOcG1N+dzJ5tN59SQ/NvVTrjwqNUxQqsygmWq/TcfGb9ONZRmyzcehYLb +m4xTjqJKQ6Kwm5SoaCYmzEb/xaeLwLS9HmR9MdB1dxtDOLpjaK/8qPECgYEArait +QhgaknlxG8pcAimPsEUrLHYWSFRE/MUk4+YvZg/5+YJ8csvY0SO2h0tF/ARwUrdI +DaLEifHm4vqgN03K/0gqj7TKxcNlV16PvVx7Vz97xejdqdHZLDfAo4lcotsgvFQW +zIqoQGGPLf6WhFixZ8mEYj8xnmzLGPvHQmf1h+8CgYEA0LDl917nIN4qw4ARPqDy +t/pXCienrcUNfgIxwSSnNwj2DdjejzI+4VNfPbW6y16BLPCp1CbUOGOwNXTj4R9H +S8Z8ESirZK5c7Tt1CyM1XlmEZ61OC43w+CsWAXz+0OiPQFLFKr+/vPXtvEjUgO7P +HG4sniKZDccNYQIl5oTOaaECgYAPU4u3AZmWw9EPutRT/IcJ75DX47Qjvgw4os2W +r4IPZ+mP88w39XW1P4mkdyg+DcY8BqD9Uxg1dHwEHEp3lw4LabsX48Thn1UaWOYm +uDrKgHfUB7FIg5S/Kkx+ImliliRVerZoZvRiejnAvW9bTtiZaFeetCUU7lUeZ1o2 +qiYpUQKBgHQDfdDhguBGPKpkJ7pVwHkJA/lyRWaN1hwplw4TvX2oH14NsHg5Q5Fd +lHqHFs2Ry/6X3bKgF0E6q4cx0V1Xnnj9sGsemlrHdiSxplDYRQql7X5OeYPGF/Bg +ZTTG8rDwy+ey6EP9BZUb03hISx/LyMynOzjGl6uOcdAcy2d9Vno0 +-----END RSA PRIVATE KEY----- diff --git a/tools/doimage/secure/kak_priv_pem.key b/tools/doimage/secure/kak_priv_pem.key new file mode 100644 index 000000000..dfceabae4 --- /dev/null +++ b/tools/doimage/secure/kak_priv_pem.key @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEowIBAAKCAQEAsj2cHcrE2pdyCqNr+oVcQULiRx6RivkrhLl2DTqWXpP33BPm +MP0W0X0z98X7E3kZO+JIGRZ8q+6AWmUpL+53aOGItNeUgT7jQKViPJIo9ZcEnv/n +PJqdgDd4xFhnwYMgq8uVYN9IPfaKDwB3EoOqjNox2JholUVxvLw6W8DAC8La3zwb +0hiqtIlirQOQ/KaTHxC6dPYkrai+jSK5uAX7Vt8RKYg5qfDxSdZckmC2xVKYURhV +bZAlyKki4h6f8CwYCJMQDpHL6mVYCuJ1Ju/OJEXvthDKD0CD2hwILhksdey3qMOC +I5lHSO1b+sTvnVHGs65wI7A+ZYwnadMNvS9e2QIDAQABAoIBAH2uu9q2FEEe8SdX +PNiWGQtbojsL7wzTzj/0lq2VVlqyc+AXmAWLMP/fDTn1vKlqhsSXNseZ96c0sgUL +uBM4T7MA9WivauQH+C6pb6/OUFt8daG4SNGPJOg4NUweGmt1jyAUmeyJBWPL6GXT +qiK//Q78/JECRxyaryyqfWwdak3flzfwONBJ03tQ9EO+L7hf9gAP7OYnAsuNp+Bz +tj1xzNMumYYYiHvsEXx8UTe8HGrmYuO53ZY5fBLGB6Jj7hRlAHNfcdVDvvoBU5cI +Zwi+5YsBuSP2Hr9Gt2Odu+KitH3gFdS0HIiDh44AT+Trj29NMANFDfkDbVHUmE0q +YBL75NECgYEA2E+fJzdaYyyPIcvQgVM8g52hltR5IRgJICND3NOdB/Zb2teBGZh+ +1XJ6ZqQMDcOQZo0CMbX9UNRnf3NU55k48/EEITxCgUJTx/WdfJeTVlWGspt5+U/r +hDnQmkePdU1en63+u9eqsla9+VhLwU3fl/pIOpsBAnoEzs3hMQZ1G0cCgYEA0vHH +ilm3AztIoZlH3wgDAl2Gu5/YopqEofKA8G4Jp89rlkk919P/GNjEc6575wjgztDB +0Xab+H7Nqxjs3HqQX/DTTuAxzAggBg3j/ijpHnmjrCHLeMT5ciyH+EH5Bg///cLq ++Cwn7aOWuSK1hGdDYxUycHylAYZXXFJzmEIEhN8CgYEA1qTrwPZkctTckyS0GiCG +g/P/TLQ6HmTDaWiVBqPVxvjn3RjLuqJf+V5Hp2JRs7bDq39xFfMJExQyP34qWkbp +BOe8uV4agDlY+ar4Q5IFWj40EzfEqWhsxCC6pt0rtbK4mqsFg1BWyfDZQnwjcAXe +QejRk5YMQnDiJHSXaRaHTjECgYAv6ecvD624ODEJM63VhRZZ5TCDUY19caeKuXB8 +LCJZUY3Ydw5rBaY92I7Wz90o3yVhFJ3RnCVVTkgdAu5aLiS5BhSZJ+dntri/Z0xQ +IK7C01JP+OUkq2kVe/Pued28eMnms+13LWBsY+oKZ03foyz1Ro1Ma6N3MzKIr9m9 +zdEE9QKBgECfoh0xE2T/cbJrtH0mwMCUM6eMVGq+yQBKNvuuPg6kaQUsah1n1rp6 +OyvjwRAXdhshszEzNTX1WTT6/i+vZX277Ax50pPo9UhQ9kVteVt1frN6+u5sy07V +fg1f2+m0iFx4BD/irU0fzSyfGE+QkBnmXFBUNSYjp2PSqYIdufmW +-----END RSA PRIVATE KEY----- diff --git a/tools/doimage/secure/sec_img_7K.cfg b/tools/doimage/secure/sec_img_7K.cfg new file mode 100644 index 000000000..459f731e1 --- /dev/null +++ b/tools/doimage/secure/sec_img_7K.cfg @@ -0,0 +1,29 @@ +# Trusted boot image extension definitions + +kak_key_file = "tools/doimage/secure/kak_priv_pem.key"; + +# CSK keys array - 16 entries total. +# Only a key with csk_key_index will be used for signing the image +# use "*" string instead of file name for specifying an empty key +csk_key_file = ["tools/doimage/secure/csk_priv_pem0.key", + "tools/doimage/secure/csk_priv_pem1.key", + "tools/doimage/secure/csk_priv_pem2.key", + "tools/doimage/secure/csk_priv_pem3.key", + "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*"]; + +# index of CSK key in the array. Valid range is 0 to 15 +csk_key_index = 3; + +# AES-256 symmetric key for image encryption +aes_key_file = "tools/doimage/secure/aes_key.txt"; + +efuse_disable = false; +jtag = { enable = true; delay = 20; }; + +box_id = 0xdeadbeef; +flash_id = 0xbaddf00d; + +# SecureBootControl and EfuseBurnControl registers array +# Two register addresses for each connected CP +# A7K - one CP, two register values +control = [0xF2441920, 0xF2441940]; diff --git a/tools/doimage/secure/sec_img_8K.cfg b/tools/doimage/secure/sec_img_8K.cfg new file mode 100644 index 000000000..a849dffde --- /dev/null +++ b/tools/doimage/secure/sec_img_8K.cfg @@ -0,0 +1,29 @@ +# Trusted boot image extension definitions + +kak_key_file = "tools/doimage/secure/kak_priv_pem.key"; + +# CSK keys array - 16 entries total. +# Only a key with csk_key_index will be used for signing the image +# use "*" string instead of file name for specifying an empty key +csk_key_file = ["tools/doimage/secure/csk_priv_pem0.key", + "tools/doimage/secure/csk_priv_pem1.key", + "tools/doimage/secure/csk_priv_pem2.key", + "tools/doimage/secure/csk_priv_pem3.key", + "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*", "*"]; + +# index of CSK key in the array. Valid range is 0 to 15 +csk_key_index = 3; + +# AES-256 symmetric key for image encryption +aes_key_file = "tools/doimage/secure/aes_key.txt"; + +efuse_disable = false; +jtag = { enable = true; delay = 20; }; + +box_id = 0xdeadbeef; +flash_id = 0xbaddf00d; + +# SecureBootControl and EfuseBurnControl registers array +# Two register addresses for each connected CP +# A8K - two CP, four register values +control = [0xF2441920, 0xF2441940, 0xF4441920, 0xF4441940]; From 1ab4df76bfecf0b3f52c8ec0ee5e102d09164b93 Mon Sep 17 00:00:00 2001 From: Christine Gharzuzi Date: Thu, 2 Aug 2018 20:25:11 +0300 Subject: [PATCH 15/17] plat: svc: ap807: add SVC configuration for AP807 - add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi Reviewed-by: Kostya Porotchkin --- include/drivers/marvell/aro.h | 1 + include/drivers/marvell/mochi/cp110_setup.h | 1 + plat/marvell/a8k/common/plat_ble_setup.c | 102 ++++++++++++++------ 3 files changed, 77 insertions(+), 27 deletions(-) diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h index 3627a201c..37e211f0f 100644 --- a/include/drivers/marvell/aro.h +++ b/include/drivers/marvell/aro.h @@ -29,6 +29,7 @@ enum cpu_clock_freq_mode { CPU_1800_DDR_1050_RCLK_1050 = 0x7, CPU_1600_DDR_900_RCLK_900 = 0x0B, CPU_1600_DDR_1050_RCLK_1050 = 0x0D, + CPU_1600_DDR_1200_RCLK_1200 = 0x0D, CPU_1600_DDR_900_RCLK_900_2 = 0x0E, CPU_1000_DDR_650_RCLK_650 = 0x13, CPU_1300_DDR_800_RCLK_800 = 0x14, diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 1c88980ae..839efe1ba 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -20,6 +20,7 @@ #define MVEBU_DEVICE_REV_MASK (0xf << MVEBU_DEVICE_REV_OFFSET) #define MVEBU_70X0_DEV_ID (0x7040) #define MVEBU_70X0_CP115_DEV_ID (0x7045) +#define MVEBU_3900_DEV_ID (0x6025) #define MVEBU_80X0_DEV_ID (0x8040) #define MVEBU_80X0_CP115_DEV_ID (0x8045) #define MVEBU_CP110_SA_DEV_ID (0x110) diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index d2607dafc..7438f69cc 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -43,11 +43,22 @@ #define AVS_EN_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x130) #define AVS_ENABLE_OFFSET (0) #define AVS_SOFT_RESET_OFFSET (2) -#define AVS_LOW_VDD_LIMIT_OFFSET (4) -#define AVS_HIGH_VDD_LIMIT_OFFSET (12) #define AVS_TARGET_DELTA_OFFSET (21) -#define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET) -#define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET) + +#ifndef MVEBU_SOC_AP807 + /* AP806 SVC bits */ + #define AVS_LOW_VDD_LIMIT_OFFSET (4) + #define AVS_HIGH_VDD_LIMIT_OFFSET (12) + #define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET) + #define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET) +#else + /* AP807 SVC bits */ + #define AVS_LOW_VDD_LIMIT_OFFSET (3) + #define AVS_HIGH_VDD_LIMIT_OFFSET (13) + #define AVS_VDD_LOW_LIMIT_MASK (0x3FF << AVS_LOW_VDD_LIMIT_OFFSET) + #define AVS_VDD_HIGH_LIMIT_MASK (0x3FF << AVS_HIGH_VDD_LIMIT_OFFSET) +#endif + /* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */ #define AVS_A7K_LOW_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \ (0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \ @@ -84,11 +95,6 @@ #define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET) /* - * - AVS work points in the LD0 eFuse: - * SVC1 work point: LD0[88:81] - * SVC2 work point: LD0[96:89] - * SVC3 work point: LD0[104:97] - * SVC4 work point: LD0[112:105] * - Identification information in the LD-0 eFuse: * DRO: LD0[74:65] - Not used by the SW * Revision: LD0[78:75] - Not used by the SW @@ -114,11 +120,30 @@ #define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */ #define EFUSE_AP_LD0_SWREV_MASK 0x7 -#define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */ -#define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */ -#define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */ +#ifndef MVEBU_SOC_AP807 + /* AP806 AVS work points in the LD0 eFuse + * SVC1 work point: LD0[88:81] + * SVC2 work point: LD0[96:89] + * SVC3 work point: LD0[104:97] + * SVC4 work point: LD0[112:105] + */ + #define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */ + #define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */ + #define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */ + #define EFUSE_AP_LD0_WP_MASK 0xFF +#else + /* AP807 AVS work points in the LD0 eFuse + * SVC1 work point: LD0[91:81] + * SVC2 work point: LD0[102:92] + * SVC3 work point: LD0[113:103] + */ + #define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */ + #define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */ + #define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */ + #define EFUSE_AP_LD0_WP_MASK 0x3FF +#endif + #define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */ -#define EFUSE_AP_LD0_WP_MASK 0xFF #define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4 @@ -233,16 +258,8 @@ static void ble_plat_svc_config(void) uint32_t reg_val, avs_workpoint, freq_pidi_mode; uint64_t efuse; uint32_t device_id, single_cluster; - uint8_t svc[4], perr[4], i, sw_ver; - - /* Due to a bug in A3900 device_id skip SVC config - * TODO: add SVC config once it is decided for a3900 - */ - if (ble_get_ap_type() == CHIP_ID_AP807) { - NOTICE("SVC: SVC is not supported on AP807\n"); - ble_plat_avs_config(); - return; - } + uint16_t svc[4], perr[4], i, sw_ver; + unsigned int ap_type; /* Set access to LD0 */ reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); @@ -276,9 +293,19 @@ static void ble_plat_svc_config(void) svc[0] = (efuse >> EFUSE_AP_LD0_SVC1_OFFS) & EFUSE_AP_LD0_WP_MASK; svc[1] = (efuse >> EFUSE_AP_LD0_SVC2_OFFS) & EFUSE_AP_LD0_WP_MASK; svc[2] = (efuse >> EFUSE_AP_LD0_SVC3_OFFS) & EFUSE_AP_LD0_WP_MASK; - svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS) & EFUSE_AP_LD0_WP_MASK; - INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n", - svc[0], svc[1], svc[2], svc[3]); + + /* Fetch AP type to distinguish between AP806 and AP807 */ + ap_type = ble_get_ap_type(); + + if (ap_type != CHIP_ID_AP807) { + svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS) + & EFUSE_AP_LD0_WP_MASK; + INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n", + svc[0], svc[1], svc[2], svc[3]); + } else { + INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n", + svc[0], svc[1], svc[2]); + } /* Validate parity of SVC workpoint values */ for (i = 0; i < 4; i++) { @@ -385,6 +412,26 @@ static void ble_plat_svc_config(void) avs_workpoint = 0; break; } + } else if (device_id == MVEBU_3900_DEV_ID) { + NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n", + "3900", freq_pidi_mode); + switch (freq_pidi_mode) { + case CPU_1600_DDR_1200_RCLK_1200: + if (perr[0]) + goto perror; + avs_workpoint = svc[0]; + break; + case CPU_1300_DDR_800_RCLK_800: + if (perr[1]) + goto perror; + avs_workpoint = svc[1]; + break; + default: + if (perr[0]) + goto perror; + avs_workpoint = svc[0]; + break; + } } else { ERROR("SVC: Unsupported Device ID 0x%x\n", device_id); return; @@ -397,7 +444,8 @@ static void ble_plat_svc_config(void) } /* Remove parity bit */ - avs_workpoint &= 0x7F; + if (ap_type != CHIP_ID_AP807) + avs_workpoint &= 0x7F; reg_val = mmio_read_32(AVS_EN_CTRL_REG); NOTICE("SVC: AVS work point changed from 0x%x to 0x%x\n", From 586714901a75a56d1ac6836f31b7ff86b339a960 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Aug 2018 10:25:24 +0300 Subject: [PATCH 16/17] plat: marvell: Update Marvell base code version to 18.09.1 Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8 Signed-off-by: Konstantin Porotchkin --- plat/marvell/version.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk index 017e11988..16b0a16aa 100644 --- a/plat/marvell/version.mk +++ b/plat/marvell/version.mk @@ -1 +1 @@ -SUBVERSION = devel-18.08.0 +SUBVERSION = devel-18.09.1 From 6d55ef1a24dc92a3b737aaa02141f550caaace06 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Thu, 16 Aug 2018 13:57:18 +0300 Subject: [PATCH 17/17] fix: tools: Fix doimage syntax breaking secure mode build Missing ")" in fprintf causing build break in secure boot mode. Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac Signed-off-by: Konstantin Porotchkin --- tools/doimage/doimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/doimage/doimage.c b/tools/doimage/doimage.c index 56dabbad4..6fc23d501 100644 --- a/tools/doimage/doimage.c +++ b/tools/doimage/doimage.c @@ -768,7 +768,7 @@ int parse_sec_config_file(char *filename) /* CSK index option */ if (config_lookup_int(&sec_cfg, "csk_key_index", &cfg_int32) != CONFIG_TRUE) { - fprintf(stderr, "Error obtaining \"flash_id\" element. " + fprintf(stderr, "Error obtaining \"flash_id\" element. "); fprintf(stderr, "Using default - 0x0\n"); cfg_int32 = 0; }