From 0943ea379f0380c0e95a606320768d63cb55b566 Mon Sep 17 00:00:00 2001 From: "Tien Hock, Loh" Date: Tue, 9 Jul 2019 13:17:04 +0800 Subject: [PATCH] plat/intel: Fix SMPLSEL for MMC MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a --- plat/intel/soc/stratix10/include/s10_system_manager.h | 5 +++++ plat/intel/soc/stratix10/soc/s10_system_manager.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h index 802386c8e..4500c6fbd 100644 --- a/plat/intel/soc/stratix10/include/s10_system_manager.h +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -59,6 +59,11 @@ #define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 #define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 +#define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) +#define SYSMGR_MMC 0x28 +#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) + + #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) void enable_nonsecure_access(void); diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c index 48f37d78d..a2ed5a3ed 100644 --- a/plat/intel/soc/stratix10/soc/s10_system_manager.c +++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c @@ -86,5 +86,8 @@ void enable_nonsecure_access(void) mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03); mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03); + + mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3)); + }