Merge pull request #1434 from soby-mathew/sm/fix_cntfrq
ARM Platforms: Update CNTFRQ register in CNTCTLBase frame
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@ -379,6 +379,7 @@
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* system level implementation of the Generic Timer.
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* system level implementation of the Generic Timer.
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******************************************************************************/
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******************************************************************************/
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#define CNTCTLBASE_CNTFRQ U(0x0)
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#define CNTNSAR 0x4
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#define CNTNSAR 0x4
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#define CNTNSAR_NS_SHIFT(x) (x)
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#define CNTNSAR_NS_SHIFT(x) (x)
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@ -390,6 +391,12 @@
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#define CNTACR_RWVT_SHIFT 0x4
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#define CNTACR_RWVT_SHIFT 0x4
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#define CNTACR_RWPT_SHIFT 0x5
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#define CNTACR_RWPT_SHIFT 0x5
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/*******************************************************************************
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* Definitions of register offsets in the CNTBaseN Frame of the
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* system level implementation of the Generic Timer.
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******************************************************************************/
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#define CNTBASE_CNTFRQ U(0x10)
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/* MAIR macros */
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/* MAIR macros */
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
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@ -554,6 +554,7 @@
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* system level implementation of the Generic Timer.
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* system level implementation of the Generic Timer.
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******************************************************************************/
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******************************************************************************/
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#define CNTCTLBASE_CNTFRQ U(0x0)
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#define CNTNSAR U(0x4)
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#define CNTNSAR U(0x4)
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#define CNTNSAR_NS_SHIFT(x) (x)
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#define CNTNSAR_NS_SHIFT(x) (x)
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@ -565,6 +566,12 @@
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#define CNTACR_RWVT_SHIFT U(0x4)
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#define CNTACR_RWVT_SHIFT U(0x4)
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#define CNTACR_RWPT_SHIFT U(0x5)
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#define CNTACR_RWPT_SHIFT U(0x5)
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/*******************************************************************************
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* Definitions of register offsets in the CNTBaseN Frame of the
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* system level implementation of the Generic Timer.
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******************************************************************************/
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#define CNTBASE_CNTFRQ U(0x10)
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/* PMCR_EL0 definitions */
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/* PMCR_EL0 definitions */
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#define PMCR_EL0_RESET_VAL U(0x0)
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#define PMCR_EL0_RESET_VAL U(0x0)
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#define PMCR_EL0_N_SHIFT U(11)
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#define PMCR_EL0_N_SHIFT U(11)
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@ -258,6 +258,8 @@
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#define ARM_SYS_CNTCTL_BASE 0x2a430000
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#define ARM_SYS_CNTCTL_BASE 0x2a430000
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#define ARM_SYS_CNTREAD_BASE 0x2a800000
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#define ARM_SYS_CNTREAD_BASE 0x2a800000
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#define ARM_SYS_TIMCTL_BASE 0x2a810000
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#define ARM_SYS_TIMCTL_BASE 0x2a810000
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#define ARM_SYS_CNT_BASE_S 0x2a820000
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#define ARM_SYS_CNT_BASE_NS 0x2a830000
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#define ARM_CONSOLE_BAUDRATE 115200
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#define ARM_CONSOLE_BAUDRATE 115200
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@ -160,6 +160,9 @@ void arm_configure_sys_timer(void)
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{
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{
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unsigned int reg_val;
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unsigned int reg_val;
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/* Read the frequency of the system counter */
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unsigned int freq_val = plat_get_syscnt_freq2();
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#if ARM_CONFIG_CNTACR
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#if ARM_CONFIG_CNTACR
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reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
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reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
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reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
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reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
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@ -169,6 +172,23 @@ void arm_configure_sys_timer(void)
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reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
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reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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/*
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* Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
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* system register initialized during psci_arch_setup() is different
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* from this and has to be updated independently.
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*/
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mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
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#ifdef PLAT_juno
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/*
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* Initialize CNTFRQ register in Non-secure CNTBase frame.
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* This is only required for Juno, because it doesn't follow ARM ARM
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* in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ.
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* Hence update the value manually.
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*/
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mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val);
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#endif
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}
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}
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#endif /* ARM_SYS_TIMCTL_BASE */
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#endif /* ARM_SYS_TIMCTL_BASE */
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