Merge changes from topic "raspberry-pi-4-support" into integration

* changes: rpi3: Do prescaler and control setup in C rpi3: Prepare for supporting a GIC (in RPi4) rpi3: Make SHARED_RAM optional rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE rpi3: Move shared rpi3 files into common directory
2019-09-16 15:17:11 +00:00 · 2019-09-16 15:17:11 +00:00 · ed01e0c407
parent f65423cd3c dcf6d4f8ed
commit ed01e0c407
16 changed files with 67 additions and 49 deletions
--- a/plat/rpi/common/include/rpi_shared.h
+++ b/plat/rpi/common/include/rpi_shared.h
@ -4,8 +4,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef RPI3_PRIVATE_H
-#define RPI3_PRIVATE_H
+#ifndef RPI_SHARED_H
+#define RPI_SHARED_H

 #include <stdint.h>

--- a/plat/rpi/common/rpi3_common.c
+++ b/plat/rpi/common/rpi3_common.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@ -17,15 +17,17 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>

 #include <rpi_hw.h>
-#include "rpi3_private.h"
+#include <rpi_shared.h>

 #define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
 					DEVICE0_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)

+#ifdef SHARED_RAM_BASE
 #define MAP_SHARED_RAM	MAP_REGION_FLAT(SHARED_RAM_BASE,		\
 					SHARED_RAM_SIZE,		\
 					MT_DEVICE | MT_RW | MT_SECURE)
+#endif

 #ifdef RPI3_PRELOADED_DTB_BASE
 #define MAP_NS_DTB	MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
@ -54,7 +56,9 @@
 */
 #ifdef IMAGE_BL1
 static const mmap_region_t plat_rpi3_mmap[] = {
+#ifdef MAP_SHARED_RAM
 	MAP_SHARED_RAM,
+#endif
 	MAP_DEVICE0,
 	MAP_FIP,
 #ifdef SPD_opteed
@ -66,7 +70,9 @@ static const mmap_region_t plat_rpi3_mmap[] = {

 #ifdef IMAGE_BL2
 static const mmap_region_t plat_rpi3_mmap[] = {
+#ifdef MAP_SHARED_RAM
 	MAP_SHARED_RAM,
+#endif
 	MAP_DEVICE0,
 	MAP_FIP,
 	MAP_NS_DRAM0,
@ -79,7 +85,9 @@ static const mmap_region_t plat_rpi3_mmap[] = {

 #ifdef IMAGE_BL31
 static const mmap_region_t plat_rpi3_mmap[] = {
+#ifdef MAP_SHARED_RAM
 	MAP_SHARED_RAM,
+#endif
 	MAP_DEVICE0,
 #ifdef RPI3_PRELOADED_DTB_BASE
 	MAP_NS_DTB,
--- a/plat/rpi/common/rpi3_image_load.c
+++ b/plat/rpi/common/rpi3_image_load.c
--- a/plat/rpi/common/rpi3_io_storage.c
+++ b/plat/rpi/common/rpi3_io_storage.c
--- a/plat/rpi/common/rpi3_pm.c
+++ b/plat/rpi/common/rpi3_pm.c
@ -17,6 +17,10 @@

 #include <rpi_hw.h>

+#ifdef RPI_HAVE_GIC
+#include <drivers/arm/gicv2.h>
+#endif
+
 /* Make composite power state parameter till power level 0 */
 #if PSCI_EXTENDED_STATE_ID

@ -112,6 +116,13 @@ static void rpi3_cpu_standby(plat_local_state_t cpu_state)
 	wfi();
 }

+static void rpi3_pwr_domain_off(const psci_power_state_t *target_state)
+{
+#ifdef RPI_HAVE_GIC
+	gicv2_cpuif_disable();
+#endif
+}
+
 /*******************************************************************************
 * Platform handler called when a power domain is about to be turned on. The
 * mpidr determines the CPU to be turned on.
@ -144,6 +155,11 @@ static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
 					PLAT_LOCAL_STATE_OFF);
+
+#ifdef RPI_HAVE_GIC
+	gicv2_pcpu_distif_init();
+	gicv2_cpuif_enable();
+#endif
 }

 /*******************************************************************************
@ -207,6 +223,7 @@ static void __dead2 rpi3_system_off(void)
 ******************************************************************************/
 static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
 	.cpu_standby = rpi3_cpu_standby,
+	.pwr_domain_off = rpi3_pwr_domain_off,
 	.pwr_domain_on = rpi3_pwr_domain_on,
 	.pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
 	.system_off = rpi3_system_off,
--- a/plat/rpi/common/rpi3_rotpk.S
+++ b/plat/rpi/common/rpi3_rotpk.S
--- a/plat/rpi/common/rpi3_stack_protector.c
+++ b/plat/rpi/common/rpi3_stack_protector.c
@ -9,7 +9,7 @@
 #include <lib/utils.h>
 #include <lib/utils_def.h>

-#include "rpi3_private.h"
+#include <drivers/rpi3/rng/rpi3_rng.h>

 /* Get 128 bits of entropy and fuse the values together to form the canary. */
 #define TRNG_NBYTES	16U
--- a/plat/rpi/common/rpi3_topology.c
+++ b/plat/rpi/common/rpi3_topology.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@ -10,7 +10,7 @@

 #include <arch.h>

-#include "rpi3_private.h"
+#include <rpi_shared.h>

 /* The power domain tree descriptor */
 static unsigned char power_domain_tree_desc[] = {
--- a/plat/rpi/common/rpi3_trusted_boot.c
+++ b/plat/rpi/common/rpi3_trusted_boot.c
--- a/plat/rpi/rpi3/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi3/aarch64/plat_helpers.S
@ -18,7 +18,6 @@
 	.globl	plat_get_my_entrypoint
 	.globl	plat_is_my_cpu_primary
 	.globl	plat_my_core_pos
-	.globl	plat_reset_handler
 	.globl	plat_rpi3_calc_core_pos
 	.globl	plat_secondary_cold_boot_setup

@ -164,16 +163,3 @@ func plat_crash_console_flush
 	mov_imm	x0, PLAT_RPI3_UART_BASE
 	b	console_16550_core_flush
 endfunc plat_crash_console_flush
-
-	/* ---------------------------------------------
-	 * void plat_reset_handler(void);
-	 * ---------------------------------------------
-	 */
-func plat_reset_handler
-	/* use the 19.2 MHz clock for the architected timer */
-	mov	x0, #RPI3_INTC_BASE_ADDRESS
-	mov	w1, #0x80000000
-	str	wzr, [x0, #RPI3_INTC_CONTROL_OFFSET]
-	str	w1, [x0, #RPI3_INTC_PRESCALER_OFFSET]
-	ret
-endfunc plat_reset_handler
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@ -110,8 +110,8 @@
 /*
 * I/O registers.
 */
-#define DEVICE0_BASE			RPI3_IO_BASE
-#define DEVICE0_SIZE			RPI3_IO_SIZE
+#define DEVICE0_BASE			RPI_IO_BASE
+#define DEVICE0_SIZE			RPI_IO_SIZE

 /*
 * Arm TF lives in SRAM, partition it here
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@ -13,14 +13,14 @@
 * Peripherals
 */

-#define RPI3_IO_BASE			ULL(0x3F000000)
-#define RPI3_IO_SIZE			ULL(0x01000000)
+#define RPI_IO_BASE			ULL(0x3F000000)
+#define RPI_IO_SIZE			ULL(0x01000000)

 /*
 * ARM <-> VideoCore mailboxes
 */
 #define RPI3_MBOX_OFFSET		ULL(0x0000B880)
-#define RPI3_MBOX_BASE			(RPI3_IO_BASE + RPI3_MBOX_OFFSET)
+#define RPI3_MBOX_BASE			(RPI_IO_BASE + RPI3_MBOX_OFFSET)
 /* VideoCore -> ARM */
 #define RPI3_MBOX0_READ_OFFSET		ULL(0x00000000)
 #define RPI3_MBOX0_PEEK_OFFSET		ULL(0x00000010)
@ -41,7 +41,7 @@
 * Power management, reset controller, watchdog.
 */
 #define RPI3_IO_PM_OFFSET		ULL(0x00100000)
-#define RPI3_PM_BASE			(RPI3_IO_BASE + RPI3_IO_PM_OFFSET)
+#define RPI3_PM_BASE			(RPI_IO_BASE + RPI3_IO_PM_OFFSET)
 /* Registers on top of RPI3_PM_BASE. */
 #define RPI3_PM_RSTC_OFFSET		ULL(0x0000001C)
 #define RPI3_PM_RSTS_OFFSET		ULL(0x00000020)
@ -62,7 +62,7 @@
 * Hardware random number generator.
 */
 #define RPI3_IO_RNG_OFFSET		ULL(0x00104000)
-#define RPI3_RNG_BASE			(RPI3_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_BASE			(RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
 #define RPI3_RNG_CTRL_OFFSET		ULL(0x00000000)
 #define RPI3_RNG_STATUS_OFFSET		ULL(0x00000004)
 #define RPI3_RNG_DATA_OFFSET		ULL(0x00000008)
@ -80,20 +80,20 @@
 * Serial port (called 'Mini UART' in the BCM docucmentation).
 */
 #define RPI3_IO_MINI_UART_OFFSET	ULL(0x00215040)
-#define RPI3_MINI_UART_BASE		(RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define RPI3_MINI_UART_BASE		(RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
 #define RPI3_MINI_UART_CLK_IN_HZ	ULL(500000000)

 /*
 * GPIO controller
 */
 #define RPI3_IO_GPIO_OFFSET		ULL(0x00200000)
-#define RPI3_GPIO_BASE			(RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET)
+#define RPI3_GPIO_BASE			(RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)

 /*
 * SDHost controller
 */
 #define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
-#define RPI3_SDHOST_BASE                (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+#define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)

 /*
 * Local interrupt controller
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@ -7,10 +7,11 @@
 include lib/libfdt/libfdt.mk
 include lib/xlat_tables_v2/xlat_tables.mk

-PLAT_INCLUDES		:=	-Iplat/rpi/rpi3/include
+PLAT_INCLUDES		:=	-Iplat/rpi/common/include		\
+				-Iplat/rpi/rpi3/include

 PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/aarch64/16550_console.S	\
-				plat/rpi/rpi3/rpi3_common.c		\
+				plat/rpi/common/rpi3_common.c		\
 				${XLAT_TABLES_LIB_SRCS}

 BL1_SOURCES		+=	drivers/io/io_fip.c			\
@ -20,7 +21,7 @@ BL1_SOURCES		+=	drivers/io/io_fip.c			\
 				plat/common/aarch64/platform_mp_stack.S	\
 				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl1_setup.c		\
-				plat/rpi/rpi3/rpi3_io_storage.c		\
+				plat/rpi/common/rpi3_io_storage.c	\
 				drivers/rpi3/mailbox/rpi3_mbox.c	\
 				plat/rpi/rpi3/rpi_mbox_board.c

@ -39,15 +40,15 @@ BL2_SOURCES		+=	common/desc_image_load.c		\
 				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \
 				plat/rpi/rpi3/rpi3_bl2_setup.c		\
-				plat/rpi/rpi3/rpi3_image_load.c		\
-				plat/rpi/rpi3/rpi3_io_storage.c
+				plat/rpi/common/rpi3_image_load.c	\
+				plat/rpi/common/rpi3_io_storage.c

 BL31_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
 				plat/common/plat_psci_common.c		\
 				plat/rpi/rpi3/aarch64/plat_helpers.S	\
 				plat/rpi/rpi3/rpi3_bl31_setup.c		\
-				plat/rpi/rpi3/rpi3_pm.c			\
-				plat/rpi/rpi3/rpi3_topology.c		\
+				plat/rpi/common/rpi3_pm.c		\
+				plat/rpi/common/rpi3_topology.c		\
 				${LIBFDT_SRCS}

 # Tune compiler for Cortex-A53
@ -160,7 +161,7 @@ endif

 ifneq ($(ENABLE_STACK_PROTECTOR), 0)
 PLAT_BL_COMMON_SOURCES	+=	drivers/rpi3/rng/rpi3_rng.c		\
-				plat/rpi/rpi3/rpi3_stack_protector.c
+				plat/rpi/common/rpi3_stack_protector.c
 endif

 ifeq (${SPD},opteed)
@ -190,13 +191,13 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
    BL1_SOURCES		+=	${AUTH_SOURCES}				\
 				bl1/tbbr/tbbr_img_desc.c		\
 				plat/common/tbbr/plat_tbbr.c		\
-				plat/rpi/rpi3/rpi3_trusted_boot.c     	\
-				plat/rpi/rpi3/rpi3_rotpk.S
+				plat/rpi/common/rpi3_trusted_boot.c    	\
+				plat/rpi/common/rpi3_rotpk.S

    BL2_SOURCES		+=	${AUTH_SOURCES}				\
 				plat/common/tbbr/plat_tbbr.c		\
-				plat/rpi/rpi3/rpi3_trusted_boot.c     	\
-				plat/rpi/rpi3/rpi3_rotpk.S
+				plat/rpi/common/rpi3_trusted_boot.c    	\
+				plat/rpi/common/rpi3_rotpk.S

    ROT_KEY             = $(BUILD_PLAT)/rot_key.pem
    ROTPK_HASH          = $(BUILD_PLAT)/rotpk_sha256.bin
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@ -10,10 +10,11 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_mmu_helpers.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>

-#include "rpi3_private.h"
+#include <rpi_shared.h>

 /* Data structure which holds the extents of the trusted SRAM for BL1 */
 static meminfo_t bl1_tzram_layout;
@ -28,6 +29,11 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
 ******************************************************************************/
 void bl1_early_platform_setup(void)
 {
+	/* use the 19.2 MHz clock for the architected timer */
+	mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0);
+	mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET,
+		      0x80000000);
+
 	/* Initialize the console to provide early debug support */
 	rpi3_console_init();

--- a/plat/rpi/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl2_setup.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@ -19,7 +19,7 @@
 #include <drivers/rpi3/gpio/rpi3_gpio.h>
 #include <drivers/rpi3/sdhost/rpi3_sdhost.h>

-#include "rpi3_private.h"
+#include <rpi_shared.h>

 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
--- a/plat/rpi/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl31_setup.c
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
@ -15,7 +15,7 @@
 #include <lib/xlat_tables/xlat_tables_defs.h>
 #include <plat/common/platform.h>

-#include "rpi3_private.h"
+#include <rpi_shared.h>

 /*
 * Placeholder variables for copying the arguments that have been passed to