rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table
Convert the DBSC QoS setting function to a simple table of register-value pairs and pass it to common rcar_qos_dbsc_setting() to write those values to matching registers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I62b133ea4f4129a641b779a782938976ad52fbfe
This commit is contained in:
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@ -18,51 +18,50 @@
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#include "qos_init_h3_v11_mstat.h"
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static void dbsc_setting(void)
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{
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struct rcar_gen3_dbsc_qos_settings h3_v11_qos[] = {
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/* BUFCAM settings */
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/* DBSC_DBCAM0CNF0 not set */
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io_write_32(DBSC_DBCAM0CNF1, 0x00044218);
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
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{ DBSC_DBCAM0CNF1, 0x00044218 },
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{ DBSC_DBCAM0CNF2, 0x000000F4 },
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/* DBSC_DBCAM0CNF3 not set */
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io_write_32(DBSC_DBSCHCNT0, 0x080F0037);
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io_write_32(DBSC_DBSCHCNT1, 0x00001010);
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io_write_32(DBSC_DBSCHSZ0, 0x00000001);
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io_write_32(DBSC_DBSCHRW0, 0x22421111);
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{ DBSC_DBSCHCNT0, 0x080F0037 },
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{ DBSC_DBSCHCNT1, 0x00001010 },
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{ DBSC_DBSCHSZ0, 0x00000001 },
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{ DBSC_DBSCHRW0, 0x22421111 },
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/* DDR3 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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{ DBSC_SCFCTST2, 0x012F1123 },
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x0000F000);
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io_write_32(DBSC_DBSCHQOS01, 0x0000E000);
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io_write_32(DBSC_DBSCHQOS02, 0x00007000);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000);
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io_write_32(DBSC_DBSCHQOS40, 0x00000E00);
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io_write_32(DBSC_DBSCHQOS41, 0x00000DFF);
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io_write_32(DBSC_DBSCHQOS42, 0x00000400);
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io_write_32(DBSC_DBSCHQOS43, 0x00000200);
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io_write_32(DBSC_DBSCHQOS90, 0x00000C00);
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io_write_32(DBSC_DBSCHQOS91, 0x00000BFF);
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io_write_32(DBSC_DBSCHQOS92, 0x00000400);
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io_write_32(DBSC_DBSCHQOS93, 0x00000200);
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io_write_32(DBSC_DBSCHQOS130, 0x00000980);
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io_write_32(DBSC_DBSCHQOS131, 0x0000097F);
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io_write_32(DBSC_DBSCHQOS132, 0x00000300);
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io_write_32(DBSC_DBSCHQOS133, 0x00000180);
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io_write_32(DBSC_DBSCHQOS140, 0x00000800);
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io_write_32(DBSC_DBSCHQOS141, 0x000007FF);
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io_write_32(DBSC_DBSCHQOS142, 0x00000300);
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io_write_32(DBSC_DBSCHQOS143, 0x00000180);
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io_write_32(DBSC_DBSCHQOS150, 0x000007D0);
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io_write_32(DBSC_DBSCHQOS151, 0x000007CF);
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io_write_32(DBSC_DBSCHQOS152, 0x000005D0);
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io_write_32(DBSC_DBSCHQOS153, 0x000003D0);
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}
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{ DBSC_DBSCHQOS00, 0x0000F000 },
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{ DBSC_DBSCHQOS01, 0x0000E000 },
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{ DBSC_DBSCHQOS02, 0x00007000 },
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{ DBSC_DBSCHQOS03, 0x00000000 },
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{ DBSC_DBSCHQOS40, 0x00000E00 },
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{ DBSC_DBSCHQOS41, 0x00000DFF },
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{ DBSC_DBSCHQOS42, 0x00000400 },
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{ DBSC_DBSCHQOS43, 0x00000200 },
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{ DBSC_DBSCHQOS90, 0x00000C00 },
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{ DBSC_DBSCHQOS91, 0x00000BFF },
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{ DBSC_DBSCHQOS92, 0x00000400 },
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{ DBSC_DBSCHQOS93, 0x00000200 },
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{ DBSC_DBSCHQOS130, 0x00000980 },
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{ DBSC_DBSCHQOS131, 0x0000097F },
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{ DBSC_DBSCHQOS132, 0x00000300 },
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{ DBSC_DBSCHQOS133, 0x00000180 },
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{ DBSC_DBSCHQOS140, 0x00000800 },
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{ DBSC_DBSCHQOS141, 0x000007FF },
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{ DBSC_DBSCHQOS142, 0x00000300 },
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{ DBSC_DBSCHQOS143, 0x00000180 },
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{ DBSC_DBSCHQOS150, 0x000007D0 },
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{ DBSC_DBSCHQOS151, 0x000007CF },
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{ DBSC_DBSCHQOS152, 0x000005D0 },
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{ DBSC_DBSCHQOS153, 0x000003D0 },
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};
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void qos_init_h3_v11(void)
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{
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dbsc_setting();
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rcar_qos_dbsc_setting(h3_v11_qos, ARRAY_SIZE(h3_v11_qos), false);
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/* DRAM Split Address mapping */
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#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
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@ -61,59 +61,52 @@
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#endif
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static void dbsc_setting(void)
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{
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/* Register write enable */
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io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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struct rcar_gen3_dbsc_qos_settings h3_v20_qos[] = {
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/* BUFCAM settings */
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io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
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io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);
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io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
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io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
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io_write_32(DBSC_DBSCHRW0, 0x22421111U);
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{ DBSC_DBCAM0CNF1, 0x00043218U },
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{ DBSC_DBCAM0CNF2, 0x000000F4U },
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{ DBSC_DBCAM0CNF3, 0x00000000U },
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{ DBSC_DBSCHCNT0, 0x000F0037U },
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{ DBSC_DBSCHSZ0, 0x00000001U },
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{ DBSC_DBSCHRW0, 0x22421111U },
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/* DDR3 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123U);
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{ DBSC_SCFCTST2, 0x012F1123U },
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
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io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
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io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
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io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
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io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
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io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
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io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
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io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
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io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
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io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
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io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
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io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
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io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
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/* Register write protect */
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io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
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}
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{ DBSC_DBSCHQOS00, 0x00000F00U },
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{ DBSC_DBSCHQOS01, 0x00000B00U },
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{ DBSC_DBSCHQOS02, 0x00000000U },
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{ DBSC_DBSCHQOS03, 0x00000000U },
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{ DBSC_DBSCHQOS40, 0x00000300U },
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{ DBSC_DBSCHQOS41, 0x000002F0U },
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{ DBSC_DBSCHQOS42, 0x00000200U },
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{ DBSC_DBSCHQOS43, 0x00000100U },
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{ DBSC_DBSCHQOS90, 0x00000100U },
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{ DBSC_DBSCHQOS91, 0x000000F0U },
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{ DBSC_DBSCHQOS92, 0x000000A0U },
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{ DBSC_DBSCHQOS93, 0x00000040U },
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{ DBSC_DBSCHQOS120, 0x00000040U },
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{ DBSC_DBSCHQOS121, 0x00000030U },
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{ DBSC_DBSCHQOS122, 0x00000020U },
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{ DBSC_DBSCHQOS123, 0x00000010U },
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{ DBSC_DBSCHQOS130, 0x00000100U },
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{ DBSC_DBSCHQOS131, 0x000000F0U },
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{ DBSC_DBSCHQOS132, 0x000000A0U },
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{ DBSC_DBSCHQOS133, 0x00000040U },
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{ DBSC_DBSCHQOS140, 0x000000C0U },
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{ DBSC_DBSCHQOS141, 0x000000B0U },
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{ DBSC_DBSCHQOS142, 0x00000080U },
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{ DBSC_DBSCHQOS143, 0x00000040U },
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{ DBSC_DBSCHQOS150, 0x00000040U },
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{ DBSC_DBSCHQOS151, 0x00000030U },
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{ DBSC_DBSCHQOS152, 0x00000020U },
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{ DBSC_DBSCHQOS153, 0x00000010U },
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};
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void qos_init_h3_v20(void)
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{
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dbsc_setting();
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rcar_qos_dbsc_setting(h3_v20_qos, ARRAY_SIZE(h3_v20_qos), true);
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/* DRAM Split Address mapping */
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#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
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@ -60,61 +60,54 @@
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#endif
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static void dbsc_setting(void)
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{
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/* Register write enable */
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io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
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/* BUFCAM settings */
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io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
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io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);
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io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
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io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
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io_write_32(DBSC_DBSCHRW0, 0x22421111U);
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{ DBSC_DBCAM0CNF1, 0x00043218U },
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{ DBSC_DBCAM0CNF2, 0x000000F4U },
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{ DBSC_DBCAM0CNF3, 0x00000000U },
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{ DBSC_DBSCHCNT0, 0x000F0037U },
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{ DBSC_DBSCHSZ0, 0x00000001U },
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{ DBSC_DBSCHRW0, 0x22421111U },
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/* DDR3 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123U);
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{ DBSC_SCFCTST2, 0x012F1123U },
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
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io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
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io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
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io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
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io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
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io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
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io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
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io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
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io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
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io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
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io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
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io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
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io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
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io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
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/* Register write protect */
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io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
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}
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{ DBSC_DBSCHQOS00, 0x00000F00U },
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{ DBSC_DBSCHQOS01, 0x00000B00U },
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{ DBSC_DBSCHQOS02, 0x00000000U },
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{ DBSC_DBSCHQOS03, 0x00000000U },
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{ DBSC_DBSCHQOS40, 0x00000300U },
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{ DBSC_DBSCHQOS41, 0x000002F0U },
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{ DBSC_DBSCHQOS42, 0x00000200U },
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{ DBSC_DBSCHQOS43, 0x00000100U },
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{ DBSC_DBSCHQOS90, 0x00000100U },
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{ DBSC_DBSCHQOS91, 0x000000F0U },
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{ DBSC_DBSCHQOS92, 0x000000A0U },
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{ DBSC_DBSCHQOS93, 0x00000040U },
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{ DBSC_DBSCHQOS120, 0x00000040U },
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{ DBSC_DBSCHQOS121, 0x00000030U },
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{ DBSC_DBSCHQOS122, 0x00000020U },
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{ DBSC_DBSCHQOS123, 0x00000010U },
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{ DBSC_DBSCHQOS130, 0x00000100U },
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{ DBSC_DBSCHQOS131, 0x000000F0U },
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{ DBSC_DBSCHQOS132, 0x000000A0U },
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{ DBSC_DBSCHQOS133, 0x00000040U },
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{ DBSC_DBSCHQOS140, 0x000000C0U },
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{ DBSC_DBSCHQOS141, 0x000000B0U },
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{ DBSC_DBSCHQOS142, 0x00000080U },
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{ DBSC_DBSCHQOS143, 0x00000040U },
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{ DBSC_DBSCHQOS150, 0x00000040U },
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{ DBSC_DBSCHQOS151, 0x00000030U },
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{ DBSC_DBSCHQOS152, 0x00000020U },
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{ DBSC_DBSCHQOS153, 0x00000010U },
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};
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void qos_init_h3_v30(void)
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{
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unsigned int split_area;
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dbsc_setting();
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rcar_qos_dbsc_setting(h3_v30_qos, ARRAY_SIZE(h3_v30_qos), true);
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#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
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split_area = 0x1BU;
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#endif
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static void dbsc_setting(void)
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{
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/* Register write enable */
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io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
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/* BUFCAM settings */
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io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
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io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);
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io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
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io_write_32(DBSC_DBSCHSZ0, 0x00000001U);
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io_write_32(DBSC_DBSCHRW0, 0x22421111U);
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{ DBSC_DBCAM0CNF1, 0x00043218U },
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{ DBSC_DBCAM0CNF2, 0x000000F4U },
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{ DBSC_DBCAM0CNF3, 0x00000000U },
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{ DBSC_DBSCHCNT0, 0x000F0037U },
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{ DBSC_DBSCHSZ0, 0x00000001U },
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{ DBSC_DBSCHRW0, 0x22421111U },
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/* DDR3 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123U);
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{ DBSC_SCFCTST2, 0x012F1123U },
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
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io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
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io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
|
||||
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
|
||||
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
|
||||
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
|
||||
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
|
||||
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
|
||||
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
|
||||
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
|
||||
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
|
||||
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
|
||||
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
|
||||
|
||||
/* Register write protect */
|
||||
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
|
||||
}
|
||||
{ DBSC_DBSCHQOS00, 0x00000F00U },
|
||||
{ DBSC_DBSCHQOS01, 0x00000B00U },
|
||||
{ DBSC_DBSCHQOS02, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS03, 0x00000000U },
|
||||
{ DBSC_DBSCHQOS40, 0x00000300U },
|
||||
{ DBSC_DBSCHQOS41, 0x000002F0U },
|
||||
{ DBSC_DBSCHQOS42, 0x00000200U },
|
||||
{ DBSC_DBSCHQOS43, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS90, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS91, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS92, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS93, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS120, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS121, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS122, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS123, 0x00000010U },
|
||||
{ DBSC_DBSCHQOS130, 0x00000100U },
|
||||
{ DBSC_DBSCHQOS131, 0x000000F0U },
|
||||
{ DBSC_DBSCHQOS132, 0x000000A0U },
|
||||
{ DBSC_DBSCHQOS133, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS140, 0x000000C0U },
|
||||
{ DBSC_DBSCHQOS141, 0x000000B0U },
|
||||
{ DBSC_DBSCHQOS142, 0x00000080U },
|
||||
{ DBSC_DBSCHQOS143, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS150, 0x00000040U },
|
||||
{ DBSC_DBSCHQOS151, 0x00000030U },
|
||||
{ DBSC_DBSCHQOS152, 0x00000020U },
|
||||
{ DBSC_DBSCHQOS153, 0x00000010U },
|
||||
};
|
||||
|
||||
void qos_init_h3n_v30(void)
|
||||
{
|
||||
unsigned int split_area;
|
||||
|
||||
dbsc_setting();
|
||||
rcar_qos_dbsc_setting(h3n_v30_qos, ARRAY_SIZE(h3n_v30_qos), true);
|
||||
|
||||
/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
|
||||
split_area = 0x1CU;
|
||||
|
|
Loading…
Reference in New Issue