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Add support for selected Cortex-A57 r0p0 errata 

This patch ensures that workarounds for erratas #806969, #813420 & #814670 that
affect Cortex-A57 r0p0 as described in the errata notice document are
implemented after every reset on each cpu.

Change-Id: I37ee16bafa623c405197925c5a0e66811d4c50ae
This commit is contained in:
Achin Gupta 2014-06-08 19:03:38 +01:00
parent c6af727f3c
commit edb3f9209c
2 changed files with 33 additions and 8 deletions
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21
include/lib/aarch64/arch.h
View File

@ -35,8 +35,12 @@
/*******************************************************************************
* MIDR bit definitions
******************************************************************************/
#define MIDR_VAR_MASK 0xf
#define MIDR_REV_MASK 0xf
#define MIDR_PN_MASK 0xfff
#define MIDR_PN_SHIFT 0x4
#define MIDR_VAR_SHIFT 20
#define MIDR_REV_SHIFT 0
#define MIDR_PN_SHIFT 4
#define MIDR_PN_AEM 0xd0f
#define MIDR_PN_A57 0xd07
#define MIDR_PN_A53 0xd03
@ -68,6 +72,7 @@
* Implementation defined sysreg encodings
******************************************************************************/
#define CPUECTLR_EL1 S3_1_C15_C2_1
#define CPUACTLR_EL1 S3_1_C15_C2_0
/*******************************************************************************
* Generic timer memory mapped registers & offsets
@ -126,9 +131,6 @@
#define SCTLR_EXCEPTION_BITS (0x3 << 6)
#define SCTLR_EE_BIT (1 << 25)
/* CPUECTLR definitions */
#define CPUECTLR_SMP_BIT (1 << 6)
/* CPACR_El1 definitions */
#define CPACR_EL1_FPEN(x) (x << 20)
#define CPACR_EL1_FP_TRAP_EL0 0x1
@ -394,6 +396,17 @@
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
/*******************************************************************************
* Imp. Def. register defines.
******************************************************************************/
/* CPUECTLR definitions */
#define CPUECTLR_SMP_BIT (1 << 6)
/* A57 CPUACTLR definitions */
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DIS_DMB_NULL (1 << 58)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************
* Definitions of register offsets and fields in the CNTCTLBase Frame of the
* system level implementation of the Generic Timer.

20
lib/aarch64/cpu_helpers.S
View File

@ -40,15 +40,27 @@ func cpu_reset_handler
* ---------------------------------------------
*/
mrs x0, midr_el1
lsr x0, x0, #MIDR_PN_SHIFT
and x0, x0, #MIDR_PN_MASK
cmp x0, #MIDR_PN_A57
lsr x1, x0, #MIDR_PN_SHIFT
and x1, x1, #MIDR_PN_MASK
cmp x1, #MIDR_PN_A57
b.eq a57_setup_begin
cmp x0, #MIDR_PN_A53
cmp x1, #MIDR_PN_A53
b.eq smp_setup_begin
b smp_setup_end
a57_setup_begin:
ubfx x1, x0, #MIDR_VAR_SHIFT, #4
cmp x1, #0 // Major Revision 0
b.ne smp_setup_begin
ubfx x1, x0, #MIDR_REV_SHIFT, #4
cmp x1, #0 // Minor Revision 0
b.ne smp_setup_begin
mov x1, #CPUACTLR_NO_ALLOC_WBWA
orr x1, x1, #CPUACTLR_DIS_DMB_NULL
orr x1, x1, #CPUACTLR_DCC_AS_DCCI
mrs x0, CPUACTLR_EL1
orr x0, x0, x1
msr CPUACTLR_EL1, x0
mov x0, #0x082
msr s3_1_c11_c0_2, x0