Merge pull request #1497 from SNG-ARM/master
RAS changes for SGI575 platform
This commit is contained in:
commit
eef90a772d
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@ -7,7 +7,6 @@
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#define __ARM_SPM_DEF_H__
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#define __ARM_SPM_DEF_H__
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#include <arm_def.h>
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#include <arm_def.h>
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#include <platform_def.h>
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#include <utils_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#include <xlat_tables_defs.h>
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@ -73,12 +72,11 @@
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/*
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/*
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* RW memory, which uses the remaining Trusted DRAM. Placed after the memory
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* RW memory, which uses the remaining Trusted DRAM. Placed after the memory
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* shared between Secure and Non-secure worlds. First there is the stack memory
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* shared between Secure and Non-secure worlds, or after the platform specific
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* for all CPUs and then there is the common heap memory. Both are mapped with
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* buffers, if defined. First there is the stack memory for all CPUs and then
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* RW permissions.
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* there is the common heap memory. Both are mapped with RW permissions.
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*/
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*/
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#define PLAT_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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#define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
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#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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@ -114,9 +114,10 @@ static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags,
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panic();
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panic();
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}
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}
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if (selected->err_record->probe) {
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ret = selected->err_record->probe(selected->err_record, &probe_data);
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ret = selected->err_record->probe(selected->err_record, &probe_data);
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assert(ret != 0);
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assert(ret != 0);
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}
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/* Call error handler for the record group */
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/* Call error handler for the record group */
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assert(selected->err_record->handler != NULL);
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assert(selected->err_record->handler != NULL);
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@ -163,4 +163,7 @@
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
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#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
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#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#endif /* __PLATFORM_DEF_H__ */
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#endif /* __PLATFORM_DEF_H__ */
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@ -5,12 +5,12 @@
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*/
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*/
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <board_arm_def.h>
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#include <console.h>
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#include <console.h>
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#include <debug.h>
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#include <debug.h>
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#include <errno.h>
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#include <errno.h>
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#include <norflash.h>
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#include <norflash.h>
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#include <platform.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <stdint.h>
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/*
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/*
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@ -8,12 +8,14 @@
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#define PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arm_def.h>
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <board_arm_def.h>
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#include <board_arm_def.h>
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#include <board_css_def.h>
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#include <board_css_def.h>
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#include <common_def.h>
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#include <common_def.h>
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#include <css_def.h>
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#include <css_def.h>
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#include <soc_css_def.h>
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#include <soc_css_def.h>
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#include <utils_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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@ -85,6 +87,55 @@
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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/* Map the secure region for access from S-EL0 */
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#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#if RAS_EXTENSION
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/* Allocate 128KB for CPER buffers */
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#define PLAT_SP_BUF_BASE ULL(0x20000)
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE + \
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PLAT_SP_BUF_BASE)
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/* Platform specific SMC FID's used for RAS */
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#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042
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#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042
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#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
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#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043
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#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
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#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044
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/* ARM SDEI dynamic shared event numbers */
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#define SGI_SDEI_DS_EVENT_0 804
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#define SGI_SDEI_DS_EVENT_1 805
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
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SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
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SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
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SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
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#define PLAT_ARM_SHARED_SDEI_EVENTS
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#define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#define ARM_SP_CPER_BUF_SIZE ULL(0x20000)
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#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \
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ARM_SP_CPER_BUF_BASE, \
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ARM_SP_CPER_BUF_BASE, \
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ARM_SP_CPER_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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#else
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#endif /* RAS_EXTENSION */
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/* Platform ID address */
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SGI_RAS__
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#define __SGI_RAS__
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/*
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* Mapping the RAS interrupt with SDEI event number and the event
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* id used with Standalone MM code
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*/
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struct sgi_ras_ev_map {
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int ras_ev_num; /* RAS Event number */
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int sdei_ev_num; /* SDEI Event number */
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int intr; /* Physical intr number */
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};
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int sgi_ras_intr_handler_setup(void);
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#endif /* __SGI_RAS__ */
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@ -8,6 +8,16 @@ ENABLE_PLAT_COMPAT := 0
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CSS_ENT_BASE := plat/arm/css/sgi
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CSS_ENT_BASE := plat/arm/css/sgi
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RAS_EXTENSION := 0
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ENABLE_SPM := 0
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SDEI_SUPPORT := 0
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EL3_EXCEPTION_HANDLING := 0
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HANDLE_EA_EL3_FIRST := 0
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INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c
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INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c
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PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
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PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
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@ -40,6 +50,10 @@ BL31_SOURCES += ${ENT_CPU_SOURCES} \
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${CSS_ENT_BASE}/sgi_topology.c \
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${CSS_ENT_BASE}/sgi_topology.c \
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${CSS_ENT_BASE}/sgi_plat_config.c
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${CSS_ENT_BASE}/sgi_plat_config.c
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ifeq (${RAS_EXTENSION},1)
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BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c
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endif
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# Add the FDT_SOURCES and options for Dynamic Config
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${CSS_ENT_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FDT_SOURCES += ${CSS_ENT_BASE}/fdts/${PLAT}_tb_fw_config.dts
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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@ -8,6 +8,7 @@
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#include <debug.h>
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#include <debug.h>
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#include <plat_arm.h>
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#include <plat_arm.h>
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#include <sgi_plat_config.h>
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#include <sgi_plat_config.h>
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#include <sgi_ras.h>
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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u_register_t arg2, u_register_t arg3)
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@ -17,3 +18,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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}
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}
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void bl31_platform_setup(void)
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{
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arm_bl31_platform_setup();
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#if RAS_EXTENSION
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sgi_ras_intr_handler_setup();
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#endif
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}
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@ -5,11 +5,14 @@
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*/
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*/
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#include <arm_def.h>
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <bl_common.h>
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#include <bl_common.h>
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#include <ccn.h>
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#include <ccn.h>
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#include <debug.h>
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#include <debug.h>
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#include <plat_arm.h>
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#include <plat_arm.h>
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#include <platform_def.h>
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#include <platform.h>
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#include <platform.h>
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#include <secure_partition.h>
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#include "../../../../bl1/bl1_private.h"
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#include "../../../../bl1/bl1_private.h"
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#if USE_COHERENT_MEM
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#if USE_COHERENT_MEM
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@ -57,6 +60,9 @@ const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_NS_DRAM1,
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ARM_MAP_NS_DRAM1,
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#if ARM_BL31_IN_DRAM
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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ARM_MAP_BL31_SEC_DRAM,
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|
#endif
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#if ENABLE_SPM
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|
ARM_SP_IMAGE_MMAP,
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#endif
|
#endif
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{0}
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{0}
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};
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};
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@ -67,8 +73,73 @@ const mmap_region_t plat_arm_mmap[] = {
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V2M_MAP_IOFPGA,
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V2M_MAP_IOFPGA,
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CSS_SGI_MAP_DEVICE,
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CSS_SGI_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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#if ENABLE_SPM
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ARM_SPM_BUF_EL3_MMAP,
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|
#endif
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{0}
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{0}
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};
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};
|
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#if ENABLE_SPM && defined(IMAGE_BL31)
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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PLAT_ARM_SECURE_MAP_DEVICE,
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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ARM_SP_CPER_BUF_MMAP,
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ARM_SP_IMAGE_RW_MMAP,
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|
ARM_SPM_BUF_EL0_MMAP,
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{0}
|
||||||
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};
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#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
|
||||||
#endif
|
#endif
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|
|
||||||
ARM_CASSERT_MMAP
|
ARM_CASSERT_MMAP
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|
|
||||||
|
#if ENABLE_SPM && defined(IMAGE_BL31)
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||||||
|
/*
|
||||||
|
* Boot information passed to a secure partition during initialisation. Linear
|
||||||
|
* indices in MP information will be filled at runtime.
|
||||||
|
*/
|
||||||
|
static secure_partition_mp_info_t sp_mp_info[] = {
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||||||
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[0] = {0x81000000, 0},
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[1] = {0x81000100, 0},
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||||||
|
[2] = {0x81000200, 0},
|
||||||
|
[3] = {0x81000300, 0},
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||||||
|
[4] = {0x81010000, 0},
|
||||||
|
[5] = {0x81010100, 0},
|
||||||
|
[6] = {0x81010200, 0},
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[7] = {0x81010300, 0},
|
||||||
|
};
|
||||||
|
|
||||||
|
const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
|
||||||
|
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
|
||||||
|
.h.version = VERSION_1,
|
||||||
|
.h.size = sizeof(secure_partition_boot_info_t),
|
||||||
|
.h.attr = 0,
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||||||
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.sp_mem_base = ARM_SP_IMAGE_BASE,
|
||||||
|
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
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.sp_image_base = ARM_SP_IMAGE_BASE,
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||||||
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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||||||
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.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
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||||||
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.sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
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||||||
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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||||||
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.sp_image_size = ARM_SP_IMAGE_SIZE,
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||||||
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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||||||
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.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
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||||||
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.sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
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||||||
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
|
||||||
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.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
|
||||||
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.num_cpus = PLATFORM_CORE_COUNT,
|
||||||
|
.mp_info = &sp_mp_info[0],
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
|
||||||
|
{
|
||||||
|
return plat_arm_secure_partition_mmap;
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
|
||||||
|
void *cookie)
|
||||||
|
{
|
||||||
|
return &plat_arm_secure_partition_boot_info;
|
||||||
|
}
|
||||||
|
#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
|
||||||
|
|
|
@ -0,0 +1,173 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arm_spm_def.h>
|
||||||
|
#include <assert.h>
|
||||||
|
#include <context_mgmt.h>
|
||||||
|
#include <interrupt_mgmt.h>
|
||||||
|
#include <mm_svc.h>
|
||||||
|
#include <ras.h>
|
||||||
|
#include <sgi_ras.h>
|
||||||
|
#include <platform.h>
|
||||||
|
#include <spm_svc.h>
|
||||||
|
#include <sdei.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
|
||||||
|
int probe_data,
|
||||||
|
const struct err_handler_data *const data);
|
||||||
|
struct efi_guid {
|
||||||
|
uint32_t data1;
|
||||||
|
uint16_t data2;
|
||||||
|
uint16_t data3;
|
||||||
|
uint8_t data4[8];
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct mm_communicate_header {
|
||||||
|
struct efi_guid header_guid;
|
||||||
|
size_t message_len;
|
||||||
|
uint8_t data[8];
|
||||||
|
} mm_communicate_header_t;
|
||||||
|
|
||||||
|
struct sgi_ras_ev_map sgi575_ras_map[] = {
|
||||||
|
|
||||||
|
/* DMC620 error overflow interrupt*/
|
||||||
|
{SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64, SGI_SDEI_DS_EVENT_1, 33},
|
||||||
|
|
||||||
|
/* DMC620 error ECC error interrupt*/
|
||||||
|
{SP_DMC_ERROR_ECC_EVENT_AARCH64, SGI_SDEI_DS_EVENT_0, 35},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map)
|
||||||
|
|
||||||
|
struct err_record_info sgi_err_records[] = {
|
||||||
|
{
|
||||||
|
.handler = &sgi_ras_intr_handler,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ras_interrupt sgi_ras_interrupts[] = {
|
||||||
|
{
|
||||||
|
.intr_number = 33,
|
||||||
|
.err_record = &sgi_err_records[0],
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.intr_number = 35,
|
||||||
|
.err_record = &sgi_err_records[0],
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
REGISTER_ERR_RECORD_INFO(sgi_err_records);
|
||||||
|
REGISTER_RAS_INTERRUPTS(sgi_ras_interrupts);
|
||||||
|
|
||||||
|
static struct sgi_ras_ev_map *plat_sgi_get_ras_ev_map(void)
|
||||||
|
{
|
||||||
|
return sgi575_ras_map;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int plat_sgi_get_ras_ev_map_size(void)
|
||||||
|
{
|
||||||
|
return SGI575_RAS_MAP_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find event mapping for a given interrupt number: On success, returns pointer
|
||||||
|
* to the event mapping. On error, returns NULL.
|
||||||
|
*/
|
||||||
|
static struct sgi_ras_ev_map *find_ras_event_map_by_intr(uint32_t intr_num)
|
||||||
|
{
|
||||||
|
struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
|
||||||
|
int i;
|
||||||
|
int size = plat_sgi_get_ras_ev_map_size();
|
||||||
|
|
||||||
|
for (i = 0; i < size; i++) {
|
||||||
|
if (map->intr == intr_num)
|
||||||
|
return map;
|
||||||
|
|
||||||
|
map++;
|
||||||
|
}
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sgi_ras_intr_configure(int intr)
|
||||||
|
{
|
||||||
|
plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3);
|
||||||
|
plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI);
|
||||||
|
plat_ic_clear_interrupt_pending(intr);
|
||||||
|
plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY,
|
||||||
|
(u_register_t)read_mpidr_el1());
|
||||||
|
plat_ic_enable_interrupt(intr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
|
||||||
|
int probe_data,
|
||||||
|
const struct err_handler_data *const data)
|
||||||
|
{
|
||||||
|
struct sgi_ras_ev_map *ras_map;
|
||||||
|
mm_communicate_header_t *header;
|
||||||
|
uint32_t intr;
|
||||||
|
|
||||||
|
cm_el1_sysregs_context_save(NON_SECURE);
|
||||||
|
intr = data->interrupt;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Find if this is a RAS interrupt. There must be an event against
|
||||||
|
* this interrupt
|
||||||
|
*/
|
||||||
|
ras_map = find_ras_event_map_by_intr(intr);
|
||||||
|
assert(ras_map);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Populate the MM_COMMUNICATE payload to share the
|
||||||
|
* event info with StandaloneMM code. This allows us to use
|
||||||
|
* MM_COMMUNICATE as a common entry mechanism into S-EL0. The
|
||||||
|
* header data will be parsed in StandaloneMM to process the
|
||||||
|
* corresponding event.
|
||||||
|
*
|
||||||
|
* TBD - Currently, the buffer allocated by SPM for communication
|
||||||
|
* between EL3 and S-EL0 is being used(PLAT_SPM_BUF_BASE). But this
|
||||||
|
* should happen via a dynamic mem allocation, which should be
|
||||||
|
* managed by SPM -- the individual platforms then call the mem
|
||||||
|
* alloc api to get memory for the payload.
|
||||||
|
*/
|
||||||
|
header = (void *) PLAT_SPM_BUF_BASE;
|
||||||
|
memset(header, 0, sizeof(*header));
|
||||||
|
memcpy(&header->data, &ras_map->ras_ev_num,
|
||||||
|
sizeof(ras_map->ras_ev_num));
|
||||||
|
header->message_len = 4;
|
||||||
|
|
||||||
|
spm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
|
||||||
|
plat_my_core_pos());
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Do an EOI of the RAS interuupt. This allows the
|
||||||
|
* sdei event to be dispatched at the SDEI event's
|
||||||
|
* priority.
|
||||||
|
*/
|
||||||
|
plat_ic_end_of_interrupt(intr);
|
||||||
|
|
||||||
|
/* Dispatch the event to the SDEI client */
|
||||||
|
sdei_dispatch_event(ras_map->sdei_ev_num);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int sgi_ras_intr_handler_setup(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map();
|
||||||
|
int size = plat_sgi_get_ras_ev_map_size();
|
||||||
|
|
||||||
|
for (i = 0; i < size; i++) {
|
||||||
|
sgi_ras_intr_configure(map->intr);
|
||||||
|
map++;
|
||||||
|
}
|
||||||
|
|
||||||
|
INFO("SGI: RAS Interrupt Handler successfully registered\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
Loading…
Reference in New Issue