Merge changes from topic "qemu_sbsa" into integration
* changes: qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1 qemu/qemu_sbsa: Adding Qemu SBSA platform
This commit is contained in:
commit
efcf951f61
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@ -0,0 +1,48 @@
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Trusted Firmware-A for QEMU SBSA target
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========================================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QEMU SBSA
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Armv8-A. While running Qemu from command line, we need to supply two Flash
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images. First Secure BootRom is supplied by -pflash argument. This Flash image
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is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu
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is responsible for Non-secure rom which also given with -pflash argument and
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contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting
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is not used
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When QEMU starts all CPUs are released simultaneously, BL1 selects a
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primary CPU to handle the boot and the secondaries are placed in a polling
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loop to be released by normal world via PSCI.
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BL2 edits the FDT, generated by QEMU at run-time to add a node describing PSCI
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and also enable methods for the CPUs.
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Current limitations:
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- Only cold boot is supported
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- No instructions for how to load a BL32 (Secure Payload)
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To build TF-A:
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::
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git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
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cd tfa
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export CROSS_COMPILE=aarch64-linux-gnu-
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make PLAT=qemu_sbsa all fip
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Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin).
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Need to copy them into top directory for EDK2 compilation.
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::
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cp build/qemu_sbsa/release/bl1.bin ../
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cp build/qemu_sbsa/release/fip.bin ../
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Those images cannot be used by itself (no semihosing support). Flash images are built by
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EDK2 build system, refer to edk2-platform repo for full build instructions.
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::
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git clone https://github.com/tianocore/edk2-platforms.git
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Platform/Qemu/SbsaQemu/Readme.md
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -41,6 +41,9 @@
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#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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/*
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* Table of regions for various BL stages to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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@ -49,6 +52,7 @@
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#ifdef IMAGE_BL1
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_FLASH0,
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MAP_FLASH1,
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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|
@ -63,6 +67,7 @@ static const mmap_region_t plat_qemu_mmap[] = {
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#ifdef IMAGE_BL2
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_FLASH0,
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MAP_FLASH1,
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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|
|
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@ -170,7 +170,7 @@
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_MMAP_REGIONS 10
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 6
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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@ -191,11 +191,13 @@
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#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
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#define QEMU_FLASH0_BASE 0x04000000
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#define QEMU_FLASH0_BASE 0x00000000
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#define QEMU_FLASH0_SIZE 0x04000000
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#define QEMU_FLASH1_BASE 0x04000000
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#define QEMU_FLASH1_SIZE 0x04000000
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#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
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#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
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#define PLAT_QEMU_FIP_BASE QEMU_FLASH1_BASE
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#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH1_SIZE
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#define DEVICE0_BASE 0x08000000
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#define DEVICE0_SIZE 0x01000000
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <tbbr_img_def.h>
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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#define QEMU_PRIMARY_CPU 0
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET 1
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF 2
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH 4
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#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
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* and secure DRAM.
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*/
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#define SEC_ROM_BASE 0x00000000
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#define SEC_ROM_SIZE 0x00020000
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#define NS_DRAM0_BASE 0x10000000000ULL
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#define NS_DRAM0_SIZE 0x00020000000
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#define SEC_SRAM_BASE 0x20000000
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#define SEC_SRAM_SIZE 0x20000000
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/*
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* RAD just placeholders, need to be chosen after finalizing mem map
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*/
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#define SEC_DRAM_BASE 0x1000
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#define SEC_DRAM_SIZE 0x1000
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/* Load pageable part of OP-TEE 2MB above secure DRAM base */
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#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000)
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#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
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/*
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* ARM-TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE SEC_SRAM_BASE
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#define SHARED_RAM_SIZE 0x00001000
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#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
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#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
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#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
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#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_QEMU_HOLD_ENTRY_SIZE)
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#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3
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#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
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#define PLAT_QEMU_HOLD_STATE_WAIT 0
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#define PLAT_QEMU_HOLD_STATE_GO 1
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#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
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#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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/*
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* BL1 specific defines.
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*
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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* Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define BL1_RO_BASE SEC_ROM_BASE
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#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
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#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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/*
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* BL2 specific defines.
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*
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE (BL31_BASE - 0x1D000)
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#define BL2_LIMIT BL31_BASE
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/*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (BL31_LIMIT - 0x20000)
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#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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/*
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* BL3-2 specific defines.
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*
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* BL3-2 can execute from Secure SRAM, or Secure DRAM.
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*/
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#define BL32_SRAM_BASE BL_RAM_BASE
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#define BL32_SRAM_LIMIT BL31_BASE
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#define BL32_DRAM_BASE SEC_DRAM_BASE
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#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
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#define BL32_MEM_BASE BL_RAM_BASE
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#define BL32_MEM_SIZE BL_RAM_SIZE
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000)
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#define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42)
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 10
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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|
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/*
|
||||
* PL011 related constants
|
||||
*/
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||||
#define UART0_BASE 0x60000000
|
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#define UART1_BASE 0x60030000
|
||||
#define UART0_CLK_IN_HZ 1
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#define UART1_CLK_IN_HZ 1
|
||||
|
||||
#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
|
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#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
|
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|
||||
#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE
|
||||
#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ
|
||||
|
||||
#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
|
||||
|
||||
#define QEMU_FLASH0_BASE 0x00000000
|
||||
#define QEMU_FLASH0_SIZE 0x10000000
|
||||
#define QEMU_FLASH1_BASE 0x10000000
|
||||
#define QEMU_FLASH1_SIZE 0x10000000
|
||||
|
||||
#define PLAT_QEMU_FIP_BASE 0x00008000
|
||||
#define PLAT_QEMU_FIP_MAX_SIZE 0x00020000
|
||||
|
||||
/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
|
||||
#define DEVICE0_BASE 0x40000000
|
||||
#define DEVICE0_SIZE 0x04080000
|
||||
/* This is map from NORMAL_UART up to SECURE_UART_MM */
|
||||
#define DEVICE1_BASE 0x60000000
|
||||
#define DEVICE1_SIZE 0x00041000
|
||||
|
||||
/*
|
||||
* GIC related constants
|
||||
* We use GICv3 where CPU Interface registers are not memory mapped
|
||||
*/
|
||||
#define GICD_BASE 0x40060000
|
||||
#define GICR_BASE 0x40080000
|
||||
#define GICC_BASE 0x0
|
||||
|
||||
#define QEMU_IRQ_SEC_SGI_0 8
|
||||
#define QEMU_IRQ_SEC_SGI_1 9
|
||||
#define QEMU_IRQ_SEC_SGI_2 10
|
||||
#define QEMU_IRQ_SEC_SGI_3 11
|
||||
#define QEMU_IRQ_SEC_SGI_4 12
|
||||
#define QEMU_IRQ_SEC_SGI_5 13
|
||||
#define QEMU_IRQ_SEC_SGI_6 14
|
||||
#define QEMU_IRQ_SEC_SGI_7 15
|
||||
|
||||
/******************************************************************************
|
||||
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
|
||||
* interrupts.
|
||||
*****************************************************************************/
|
||||
#define PLATFORM_G1S_PROPS(grp) \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define PLATFORM_G0_PROPS(grp)
|
||||
|
||||
/*
|
||||
* DT related constants
|
||||
*/
|
||||
#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
|
||||
#define PLAT_QEMU_DT_MAX_SIZE 0x10000
|
||||
|
||||
/*
|
||||
* System counter
|
||||
*/
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
|
||||
|
||||
#endif /* __PLATFORM_DEF_H__ */
|
|
@ -0,0 +1,101 @@
|
|||
#
|
||||
# Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
CRASH_REPORTING := 1
|
||||
|
||||
include lib/libfdt/libfdt.mk
|
||||
|
||||
# Enable new version of image loading on QEMU platforms
|
||||
LOAD_IMAGE_V2 := 1
|
||||
|
||||
ifeq ($(NEED_BL32),yes)
|
||||
$(eval $(call add_define,QEMU_LOAD_BL32))
|
||||
endif
|
||||
|
||||
PLAT_QEMU_PATH := plat/qemu/qemu_sbsa
|
||||
PLAT_QEMU_COMMON_PATH := plat/qemu/common
|
||||
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
|
||||
-I${PLAT_QEMU_COMMON_PATH}/include \
|
||||
-I${PLAT_QEMU_PATH}/include \
|
||||
-Iinclude/common/tbbr
|
||||
|
||||
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_console.c \
|
||||
drivers/arm/pl011/${ARCH}/pl011_console.S
|
||||
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
|
||||
|
||||
BL1_SOURCES += drivers/io/io_semihosting.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_memmap.c \
|
||||
lib/semihosting/semihosting.c \
|
||||
lib/semihosting/${ARCH}/semihosting_call.S \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
|
||||
|
||||
BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a57.S
|
||||
|
||||
BL2_SOURCES += drivers/io/io_semihosting.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_memmap.c \
|
||||
lib/semihosting/semihosting.c \
|
||||
lib/semihosting/${ARCH}/semihosting_call.S \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \
|
||||
common/fdt_fixup.c \
|
||||
$(LIBFDT_SRCS)
|
||||
ifeq (${LOAD_IMAGE_V2},1)
|
||||
BL2_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \
|
||||
common/desc_image_load.c
|
||||
endif
|
||||
|
||||
QEMU_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
|
||||
drivers/arm/gic/v3/gicv3_main.c \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
plat/common/plat_gicv3.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a57.S \
|
||||
plat/common/plat_psci_common.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/topology.c \
|
||||
${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
|
||||
${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
|
||||
${QEMU_GIC_SOURCES}
|
||||
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
ENABLE_STACK_PROTECTOR := 0
|
||||
ifneq ($(ENABLE_STACK_PROTECTOR), 0)
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
|
||||
endif
|
||||
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
# Disable the PSCI platform compatibility layer
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
# Use known base for UEFI if not given from command line
|
||||
# By default BL33 is at FLASH1 base
|
||||
PRELOADED_BL33_BASE ?= 0x10000000
|
||||
|
||||
# Qemu SBSA plafrom only support SEC_SRAM
|
||||
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
|
||||
$(eval $(call add_define,BL32_RAM_LOCATION_ID))
|
||||
|
||||
# Do not enable SVE
|
||||
ENABLE_SVE_FOR_NS := 0
|
Loading…
Reference in New Issue