plat/css: allow platforms to define the system power domain level
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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@ -11,9 +11,6 @@
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#include <psci.h>
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#include <stdint.h>
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/* System power domain at level 2, as currently implemented by CSS platforms */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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/* Macros to read the CSS power domain state */
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#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
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#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
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@ -292,4 +292,7 @@
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
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#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#endif /* PLATFORM_DEF_H */
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@ -32,6 +32,8 @@
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N1SDP_MAX_CPUS_PER_CLUSTER * \
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N1SDP_MAX_PE_PER_CPU)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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@ -20,4 +20,7 @@
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#define SGI575_DMC620_BASE0 UL(0x4e000000)
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#define SGI575_DMC620_BASE1 UL(0x4e100000)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#endif /* PLATFORM_DEF_H */
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@ -20,4 +20,7 @@
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#define SGICLARKA_DMC620_BASE0 UL(0x4e000000)
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#define SGICLARKA_DMC620_BASE1 UL(0x4e100000)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#endif /* PLATFORM_DEF_H */
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@ -239,4 +239,8 @@
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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#endif /* SGM_BASE_PLATFORM_DEF_H */
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