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plat: renesas: rcar: include: Code cleanup 

This patch fixes checkpatch warnings and replaces TAB with
space after #define macros.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
This commit is contained in:
Biju Das 2020-12-13 20:49:27 +00:00
parent 157c4fcafd
commit f020963999
4 changed files with 270 additions and 261 deletions
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24
plat/renesas/rcar/include/platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -97,11 +97,13 @@
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
/*******************************************************************************
/*
******************************************************************************
* BL2 specific defines.
******************************************************************************/
/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth. */
******************************************************************************
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
#define BL2_LIMIT U(0xE6320000)
@ -121,11 +123,13 @@
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/*******************************************************************************
/*
******************************************************************************
* BL31 specific defines.
******************************************************************************/
/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth. */
******************************************************************************
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE)
@ -176,7 +180,7 @@
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* caches. Such alignment ensures that two mailboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.

20
plat/renesas/rcar/include/rcar_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -47,15 +47,19 @@
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
RCAR_SHARED_MEM_SIZE - 0x100)
/* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU */
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU
*/
#if USE_COHERENT_MEM
#define RCAR_BL_REGIONS (3)
#else
#define RCAR_BL_REGIONS (2)
#endif
/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c. */
/*
* The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c.
*/
#if IMAGE_BL2
#define RCAR_MMAP_ENTRIES (9)
#endif
@ -75,7 +79,7 @@
/* BL31 */
#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
#define RCAR_DEVICE_SIZE (0x1A000000)
#define RCAR_LOG_RES_SIZE (512/8)
#define RCAR_LOG_RES_SIZE (64)
#define RCAR_LOG_HEADER_SIZE (16)
#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
RCAR_LOG_RES_SIZE)
@ -139,8 +143,8 @@
#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */

11
plat/renesas/rcar/include/rcar_private.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,12 +7,12 @@
#ifndef RCAR_PRIVATE_H
#define RCAR_PRIVATE_H
#include <platform_def.h>
#include <common/bl_common.h>
#include <lib/bakery_lock.h>
#include <lib/el3_runtime/cpu_data.h>
#include <platform_def.h>
typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t;
@ -69,10 +69,11 @@ typedef struct rcar_cpu_data {
#define rcar_lock_release(_lock_arg) \
bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
/* Ensure that the size of the RCAR specific per-cpu data structure and the size
/*
* Ensure that the size of the RCAR specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same
*/
CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t),
CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
rcar_pcpu_data_size_mismatch);
#endif
/*

2
plat/renesas/rcar/include/registers/lifec_registers.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/