From ee4c70ebb98ac7e73537cdcb81cd88c443557850 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Mar 2021 16:34:45 +0100 Subject: [PATCH 1/3] drivers: marvell: comphy-a3700: Fix configuring polarity invert bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Signed-off-by: Pali Rohár Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b --- drivers/marvell/comphy/phy-comphy-3700.c | 35 ++++++++++++++---------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index f6a40a587..04e3ae561 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -525,7 +525,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, data |= TXD_INVERT_BIT; if (invert & COMPHY_POLARITY_RXD_INVERT) data |= RXD_INVERT_BIT; - reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0); + mask = TXD_INVERT_BIT | RXD_INVERT_BIT; + reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); /* * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to @@ -746,12 +747,15 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, /* * 13. Check the Polarity invert bit */ - if (invert & COMPHY_POLARITY_TXD_INVERT) - usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT, - TXD_INVERT_BIT, mode); - if (invert & COMPHY_POLARITY_RXD_INVERT) - usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT, - RXD_INVERT_BIT, mode); + data = 0U; + if (invert & COMPHY_POLARITY_TXD_INVERT) { + data |= TXD_INVERT_BIT; + } + if (invert & COMPHY_POLARITY_RXD_INVERT) { + data |= RXD_INVERT_BIT; + } + mask = TXD_INVERT_BIT | RXD_INVERT_BIT; + usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode); /* * 14. Set max speed generation to USB3.0 5Gbps @@ -802,6 +806,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, { int ret; uint32_t ref_clk; + uint32_t mask, data; int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode); debug_enter(); @@ -858,13 +863,15 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK); /* 10. Check the Polarity invert bit */ - if (invert & COMPHY_POLARITY_TXD_INVERT) - reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, - TXD_INVERT_BIT, 0x0); - - if (invert & COMPHY_POLARITY_RXD_INVERT) - reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, - RXD_INVERT_BIT, 0x0); + data = 0U; + if (invert & COMPHY_POLARITY_TXD_INVERT) { + data |= TXD_INVERT_BIT; + } + if (invert & COMPHY_POLARITY_RXD_INVERT) { + data |= RXD_INVERT_BIT; + } + mask = TXD_INVERT_BIT | RXD_INVERT_BIT; + reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* 11. Release SW reset */ reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, From ccec1bd5ca37c4a8b74d9ce9e2931da95f987bc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Mar 2021 16:40:46 +0100 Subject: [PATCH 2/3] drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The third argument of the reg_set() function has name 'mask', which indicates that it is a mask applied to the register value which is going to be updated. But the implementation of this function uses this argument to clear prior value of the register, i.e. instead of new_val = (old_val & ~mask) | (data & mask); it does new_val = (new_val & ~mask) | data; (The more proper name for this function should be reg_clrsetbits(), since internally it calls mmio_clrsetbits_32().) To make code more readable set 'mask' argument to real mask, i.e. bits of register values which are going to be updated. This patch does not make any functional change, only cosmetic, due to how 'mask' is interpreted. Signed-off-by: Pali Rohár Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65 --- drivers/marvell/comphy/phy-comphy-3700.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 04e3ae561..df8c4110d 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -564,7 +564,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index, * refer to RX initialization part for details. */ reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), - PHY_RX_INIT_BIT, 0x0); + PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_STATUS_OFFSET(comphy_index), @@ -595,7 +595,7 @@ static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index) debug_enter(); data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT; - mask = 0; + mask = data; offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); reg_set(offset, data, mask); @@ -813,15 +813,15 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, /* 1. Enable max PLL. */ reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, - USE_MAX_PLL_RATE_EN, 0x0); + USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); /* 2. Select 20 bit SERDES interface. */ reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, - CFG_SEL_20B, 0); + CFG_SEL_20B, CFG_SEL_20B); /* 3. Force to use reg setting for PCIe mode */ reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, - SEL_BITS_PCIE_FORCE, 0); + SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); /* 4. Change RX wait */ reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, From 40d08192aad13c04b5da55a625b76878406711d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 24 Mar 2021 17:03:43 +0100 Subject: [PATCH 3/3] drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Both U-Boot and Linux kernel support only Root Complex mode. Set this bit. Signed-off-by: Pali Rohár Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7 --- drivers/marvell/comphy/phy-comphy-3700.c | 2 +- drivers/marvell/comphy/phy-comphy-3700.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index df8c4110d..02fe97c2a 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -835,7 +835,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index, /* 6. Enable the output of 100M/125M/500M clock */ reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, - MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN, + MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, REG_16_BIT_MASK); /* diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h index 1628e36ce..94056f18d 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.h +++ b/drivers/marvell/comphy/phy-comphy-3700.h @@ -104,6 +104,7 @@ enum { #define COMPHY_MISC_REG0_ADDR 0x4F #define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit)) #define CLK100M_125M_EN BIT(4) +#define TXDCLK_2X_SEL BIT(6) #define CLK500M_EN BIT(7) #define PHY_REF_CLK_SEL BIT(10) #define MISC_REG0_DEFAULT_VALUE 0xA00D