Merge "Implement workaround for AT speculative behaviour" into integration
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commit
f0fea132e4
2
Makefile
2
Makefile
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@ -891,6 +891,7 @@ $(eval $(call assert_boolean,BL2_INV_DCACHE))
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$(eval $(call assert_boolean,USE_SPINLOCK_CAS))
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$(eval $(call assert_boolean,ENCRYPT_BL31))
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$(eval $(call assert_boolean,ENCRYPT_BL32))
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$(eval $(call assert_boolean,ERRATA_SPECULATIVE_AT))
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$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
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$(eval $(call assert_numeric,ARM_ARCH_MINOR))
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@ -967,6 +968,7 @@ $(eval $(call add_define,BL2_AT_EL3))
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$(eval $(call add_define,BL2_IN_XIP_MEM))
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$(eval $(call add_define,BL2_INV_DCACHE))
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$(eval $(call add_define,USE_SPINLOCK_CAS))
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$(eval $(call add_define,ERRATA_SPECULATIVE_AT))
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ifeq (${SANITIZE_UB},trap)
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$(eval $(call add_define,MONITOR_TRAPS))
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@ -673,6 +673,29 @@ Common build options
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default value of this flag is ``no``. Note this option must be enabled only
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for ARM architecture greater than Armv8.5-A.
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- ``ERRATA_SPECULATIVE_AT``: This flag enables/disables page table walk during
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context restore as speculative AT instructions using an out-of-context
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translation regime could cause subsequent requests to generate an incorrect
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translation.
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System registers are not updated during context save, hence this workaround
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need not be applied in the context save path.
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This boolean option enables errata for all below CPUs.
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+---------+--------------+
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| Errata | CPU |
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+=========+==============+
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| 1165522 | Cortex-A76 |
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+---------+--------------+
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| 1319367 | Cortex-A72 |
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+---------+--------------+
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| 1319537 | Cortex-A57 |
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+---------+--------------+
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| 1530923 | Cortex-A55 |
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+---------+--------------+
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| 1530924 | Cortex-A53 |
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+---------+--------------+
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GICv3 driver options
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--------------------
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@ -381,6 +381,7 @@
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/* HCR definitions */
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#define HCR_API_BIT (ULL(1) << 41)
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#define HCR_APK_BIT (ULL(1) << 40)
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#define HCR_E2H_BIT (ULL(1) << 34)
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#define HCR_TGE_BIT (ULL(1) << 27)
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#define HCR_RW_SHIFT U(31)
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#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
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@ -234,6 +234,21 @@ endfunc el2_sysregs_context_save
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*/
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func el2_sysregs_context_restore
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#if ERRATA_SPECULATIVE_AT
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/* Clear EPD0 and EPD1 bit and M bit to disable PTW */
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mrs x9, hcr_el2
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tst x9, #HCR_E2H_BIT
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bne 1f
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mrs x9, tcr_el2
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orr x9, x9, #TCR_EPD0_BIT
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orr x9, x9, #TCR_EPD1_BIT
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msr tcr_el2, x9
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1: mrs x9, sctlr_el2
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bic x9, x9, #SCTLR_M_BIT
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msr sctlr_el2, x9
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isb
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#endif
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ldp x9, x10, [x0, #CTX_ACTLR_EL2]
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msr actlr_el2, x9
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msr afsr0_el2, x10
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@ -282,17 +297,15 @@ func el2_sysregs_context_restore
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msr mair_el2, x15
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msr mdcr_el2, x16
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ldp x17, x9, [x0, #CTX_PMSCR_EL2]
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ldr x17, [x0, #CTX_PMSCR_EL2]
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msr PMSCR_EL2, x17
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msr sctlr_el2, x9
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ldp x10, x11, [x0, #CTX_SPSR_EL2]
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msr spsr_el2, x10
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msr sp_el2, x11
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ldp x12, x13, [x0, #CTX_TCR_EL2]
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msr tcr_el2, x12
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msr tpidr_el2, x13
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ldr x12, [x0, #CTX_TPIDR_EL2]
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msr tpidr_el2, x12
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ldp x14, x15, [x0, #CTX_TTBR0_EL2]
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msr ttbr0_el2, x14
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@ -404,6 +417,19 @@ func el2_sysregs_context_restore
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msr scxtnum_el2, x9
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#endif
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#if ERRATA_SPECULATIVE_AT
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/*
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* Make sure all registers are stored successfully except
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* SCTLR_EL2 and TCR_EL2
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*/
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isb
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#endif
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ldr x9, [x0, #CTX_SCTLR_EL2]
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msr sctlr_el2, x9
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ldr x9, [x0, #CTX_TCR_EL2]
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msr tcr_el2, x9
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ret
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endfunc el2_sysregs_context_restore
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@ -515,12 +541,22 @@ endfunc el1_sysregs_context_save
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*/
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func el1_sysregs_context_restore
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#if ERRATA_SPECULATIVE_AT
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mrs x9, tcr_el1
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orr x9, x9, #TCR_EPD0_BIT
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orr x9, x9, #TCR_EPD1_BIT
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msr tcr_el1, x9
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mrs x9, sctlr_el1
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bic x9, x9, #SCTLR_M_BIT
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msr sctlr_el1, x9
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isb
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#endif
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ldp x9, x10, [x0, #CTX_SPSR_EL1]
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msr spsr_el1, x9
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msr elr_el1, x10
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ldp x15, x16, [x0, #CTX_SCTLR_EL1]
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msr sctlr_el1, x15
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ldr x16, [x0, #CTX_ACTLR_EL1]
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msr actlr_el1, x16
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ldp x17, x9, [x0, #CTX_CPACR_EL1]
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@ -539,9 +575,8 @@ func el1_sysregs_context_restore
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msr mair_el1, x14
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msr amair_el1, x15
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ldp x16, x17, [x0, #CTX_TCR_EL1]
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msr tcr_el1, x16
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msr tpidr_el1, x17
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ldr x16,[x0, #CTX_TPIDR_EL1]
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msr tpidr_el1, x16
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ldp x9, x10, [x0, #CTX_TPIDR_EL0]
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msr tpidr_el0, x9
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@ -597,6 +632,19 @@ func el1_sysregs_context_restore
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msr GCR_EL1, x14
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#endif
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#if ERRATA_SPECULATIVE_AT
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/*
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* Make sure all registers are stored successfully except
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* SCTLR_EL1 and TCR_EL1
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*/
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isb
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#endif
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ldr x9, [x0, #CTX_SCTLR_EL1]
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msr sctlr_el1, x9
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ldr x9, [x0, #CTX_TCR_EL1]
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msr tcr_el1, x9
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/* No explict ISB required here as ERET covers it */
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ret
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endfunc el1_sysregs_context_restore
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@ -293,3 +293,6 @@ CTX_INCLUDE_EL2_REGS := 0
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# than Armv8.5-A
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# By default it is set to "no"
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SUPPORT_STACK_MEMTAG := no
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# Select workaround for AT speculative behaviour.
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ERRATA_SPECULATIVE_AT := 0
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