Merge "Fix exception in save/restore of EL2 registers." into integration
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
f1a1653ce1
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@ -168,76 +168,75 @@
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#define CTX_ELR_EL2 U(0x58)
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#define CTX_ESR_EL2 U(0x60)
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#define CTX_FAR_EL2 U(0x68)
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#define CTX_FPEXC32_EL2 U(0x70)
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#define CTX_HACR_EL2 U(0x78)
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#define CTX_HCR_EL2 U(0x80)
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#define CTX_HPFAR_EL2 U(0x88)
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#define CTX_HSTR_EL2 U(0x90)
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#define CTX_ICC_SRE_EL2 U(0x98)
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#define CTX_ICH_HCR_EL2 U(0xa0)
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#define CTX_ICH_VMCR_EL2 U(0xa8)
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#define CTX_MAIR_EL2 U(0xb0)
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#define CTX_MDCR_EL2 U(0xb8)
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#define CTX_PMSCR_EL2 U(0xc0)
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#define CTX_SCTLR_EL2 U(0xc8)
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#define CTX_SPSR_EL2 U(0xd0)
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#define CTX_SP_EL2 U(0xd8)
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#define CTX_TCR_EL2 U(0xe0)
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#define CTX_TPIDR_EL2 U(0xe8)
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#define CTX_TTBR0_EL2 U(0xf0)
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#define CTX_VBAR_EL2 U(0xf8)
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#define CTX_VMPIDR_EL2 U(0x100)
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#define CTX_VPIDR_EL2 U(0x108)
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#define CTX_VTCR_EL2 U(0x110)
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#define CTX_VTTBR_EL2 U(0x118)
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#define CTX_HACR_EL2 U(0x70)
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#define CTX_HCR_EL2 U(0x78)
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#define CTX_HPFAR_EL2 U(0x80)
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#define CTX_HSTR_EL2 U(0x88)
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#define CTX_ICC_SRE_EL2 U(0x90)
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#define CTX_ICH_HCR_EL2 U(0x98)
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#define CTX_ICH_VMCR_EL2 U(0xa0)
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#define CTX_MAIR_EL2 U(0xa8)
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#define CTX_MDCR_EL2 U(0xb0)
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#define CTX_PMSCR_EL2 U(0xb8)
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#define CTX_SCTLR_EL2 U(0xc0)
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#define CTX_SPSR_EL2 U(0xc8)
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#define CTX_SP_EL2 U(0xd0)
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#define CTX_TCR_EL2 U(0xd8)
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#define CTX_TPIDR_EL2 U(0xe0)
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#define CTX_TTBR0_EL2 U(0xe8)
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#define CTX_VBAR_EL2 U(0xf0)
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#define CTX_VMPIDR_EL2 U(0xf8)
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#define CTX_VPIDR_EL2 U(0x100)
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#define CTX_VTCR_EL2 U(0x108)
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#define CTX_VTTBR_EL2 U(0x110)
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// Only if MTE registers in use
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#define CTX_TFSR_EL2 U(0x120)
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#define CTX_TFSR_EL2 U(0x118)
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// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
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#define CTX_MPAM2_EL2 U(0x128)
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#define CTX_MPAMHCR_EL2 U(0x130)
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#define CTX_MPAMVPM0_EL2 U(0x138)
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#define CTX_MPAMVPM1_EL2 U(0x140)
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#define CTX_MPAMVPM2_EL2 U(0x148)
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#define CTX_MPAMVPM3_EL2 U(0x150)
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#define CTX_MPAMVPM4_EL2 U(0x158)
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#define CTX_MPAMVPM5_EL2 U(0x160)
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#define CTX_MPAMVPM6_EL2 U(0x168)
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#define CTX_MPAMVPM7_EL2 U(0x170)
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#define CTX_MPAMVPMV_EL2 U(0x178)
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#define CTX_MPAM2_EL2 U(0x120)
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#define CTX_MPAMHCR_EL2 U(0x128)
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#define CTX_MPAMVPM0_EL2 U(0x130)
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#define CTX_MPAMVPM1_EL2 U(0x138)
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#define CTX_MPAMVPM2_EL2 U(0x140)
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#define CTX_MPAMVPM3_EL2 U(0x148)
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#define CTX_MPAMVPM4_EL2 U(0x150)
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#define CTX_MPAMVPM5_EL2 U(0x158)
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#define CTX_MPAMVPM6_EL2 U(0x160)
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#define CTX_MPAMVPM7_EL2 U(0x168)
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#define CTX_MPAMVPMV_EL2 U(0x170)
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// Starting with Armv8.6
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#define CTX_HAFGRTR_EL2 U(0x180)
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#define CTX_HDFGRTR_EL2 U(0x188)
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#define CTX_HDFGWTR_EL2 U(0x190)
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#define CTX_HFGITR_EL2 U(0x198)
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#define CTX_HFGRTR_EL2 U(0x1a0)
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#define CTX_HFGWTR_EL2 U(0x1a8)
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#define CTX_CNTPOFF_EL2 U(0x1b0)
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#define CTX_HAFGRTR_EL2 U(0x178)
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#define CTX_HDFGRTR_EL2 U(0x180)
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#define CTX_HDFGWTR_EL2 U(0x188)
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#define CTX_HFGITR_EL2 U(0x190)
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#define CTX_HFGRTR_EL2 U(0x198)
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#define CTX_HFGWTR_EL2 U(0x1a0)
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#define CTX_CNTPOFF_EL2 U(0x1a8)
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// Starting with Armv8.4
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#define CTX_CNTHPS_CTL_EL2 U(0x1b8)
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#define CTX_CNTHPS_CVAL_EL2 U(0x1c0)
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#define CTX_CNTHPS_TVAL_EL2 U(0x1c8)
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#define CTX_CNTHVS_CTL_EL2 U(0x1d0)
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#define CTX_CNTHVS_CVAL_EL2 U(0x1d8)
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#define CTX_CNTHVS_TVAL_EL2 U(0x1e0)
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#define CTX_CNTHV_CTL_EL2 U(0x1e8)
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#define CTX_CNTHV_CVAL_EL2 U(0x1f0)
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#define CTX_CNTHV_TVAL_EL2 U(0x1f8)
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#define CTX_CONTEXTIDR_EL2 U(0x200)
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#define CTX_SDER32_EL2 U(0x208)
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#define CTX_TTBR1_EL2 U(0x210)
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#define CTX_VDISR_EL2 U(0x218)
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#define CTX_VNCR_EL2 U(0x220)
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#define CTX_VSESR_EL2 U(0x228)
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#define CTX_VSTCR_EL2 U(0x230)
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#define CTX_VSTTBR_EL2 U(0x238)
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#define CTX_TRFCR_EL2 U(0x240)
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#define CTX_CNTHPS_CTL_EL2 U(0x1b0)
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#define CTX_CNTHPS_CVAL_EL2 U(0x1b8)
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#define CTX_CNTHPS_TVAL_EL2 U(0x1c0)
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#define CTX_CNTHVS_CTL_EL2 U(0x1c8)
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#define CTX_CNTHVS_CVAL_EL2 U(0x1d0)
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#define CTX_CNTHVS_TVAL_EL2 U(0x1d8)
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#define CTX_CNTHV_CTL_EL2 U(0x1e0)
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#define CTX_CNTHV_CVAL_EL2 U(0x1e8)
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#define CTX_CNTHV_TVAL_EL2 U(0x1f0)
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#define CTX_CONTEXTIDR_EL2 U(0x1f8)
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#define CTX_SDER32_EL2 U(0x200)
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#define CTX_TTBR1_EL2 U(0x208)
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#define CTX_VDISR_EL2 U(0x210)
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#define CTX_VNCR_EL2 U(0x218)
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#define CTX_VSESR_EL2 U(0x220)
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#define CTX_VSTCR_EL2 U(0x228)
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#define CTX_VSTTBR_EL2 U(0x230)
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#define CTX_TRFCR_EL2 U(0x238)
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// Starting with Armv8.5
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#define CTX_SCXTNUM_EL2 U(0x248)
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#define CTX_SCXTNUM_EL2 U(0x240)
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/* Align to the next 16 byte boundary */
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#define CTX_EL2_SYSREGS_END U(0x250)
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@ -71,53 +71,52 @@ func el2_sysregs_context_save
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mrs x15, far_el2
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stp x14, x15, [x0, #CTX_ESR_EL2]
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mrs x16, fpexc32_el2
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mrs x17, hacr_el2
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stp x16, x17, [x0, #CTX_FPEXC32_EL2]
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mrs x16, hacr_el2
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mrs x17, hcr_el2
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stp x16, x17, [x0, #CTX_HACR_EL2]
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mrs x9, hcr_el2
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mrs x10, hpfar_el2
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stp x9, x10, [x0, #CTX_HCR_EL2]
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mrs x9, hpfar_el2
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mrs x10, hstr_el2
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stp x9, x10, [x0, #CTX_HPFAR_EL2]
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mrs x11, hstr_el2
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mrs x12, ICC_SRE_EL2
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stp x11, x12, [x0, #CTX_HSTR_EL2]
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mrs x11, ICC_SRE_EL2
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mrs x12, ICH_HCR_EL2
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stp x11, x12, [x0, #CTX_ICC_SRE_EL2]
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mrs x13, ICH_HCR_EL2
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mrs x14, ICH_VMCR_EL2
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stp x13, x14, [x0, #CTX_ICH_HCR_EL2]
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mrs x13, ICH_VMCR_EL2
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mrs x14, mair_el2
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stp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
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mrs x15, mair_el2
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mrs x16, mdcr_el2
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stp x15, x16, [x0, #CTX_MAIR_EL2]
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mrs x15, mdcr_el2
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mrs x16, PMSCR_EL2
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stp x15, x16, [x0, #CTX_MDCR_EL2]
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mrs x17, PMSCR_EL2
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mrs x9, sctlr_el2
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stp x17, x9, [x0, #CTX_PMSCR_EL2]
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mrs x17, sctlr_el2
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mrs x9, spsr_el2
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stp x17, x9, [x0, #CTX_SCTLR_EL2]
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mrs x10, spsr_el2
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mrs x11, sp_el2
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stp x10, x11, [x0, #CTX_SPSR_EL2]
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mrs x10, sp_el2
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mrs x11, tcr_el2
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stp x10, x11, [x0, #CTX_SP_EL2]
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mrs x12, tcr_el2
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mrs x13, tpidr_el2
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stp x12, x13, [x0, #CTX_TCR_EL2]
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mrs x12, tpidr_el2
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mrs x13, ttbr0_el2
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stp x12, x13, [x0, #CTX_TPIDR_EL2]
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mrs x14, ttbr0_el2
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mrs x15, vbar_el2
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stp x14, x15, [x0, #CTX_TTBR0_EL2]
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mrs x14, vbar_el2
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mrs x15, vmpidr_el2
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stp x14, x15, [x0, #CTX_VBAR_EL2]
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mrs x16, vmpidr_el2
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mrs x17, vpidr_el2
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stp x16, x17, [x0, #CTX_VMPIDR_EL2]
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mrs x16, vpidr_el2
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mrs x17, vtcr_el2
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stp x16, x17, [x0, #CTX_VPIDR_EL2]
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mrs x9, vtcr_el2
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mrs x10, vttbr_el2
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stp x9, x10, [x0, #CTX_VTCR_EL2]
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mrs x9, vttbr_el2
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str x9, [x0, #CTX_VTTBR_EL2]
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#if CTX_INCLUDE_MTE_REGS
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mrs x11, TFSR_EL2
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str x11, [x0, #CTX_TFSR_EL2]
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mrs x10, TFSR_EL2
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str x10, [x0, #CTX_TFSR_EL2]
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#endif
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#if ENABLE_MPAM_FOR_LOWER_ELS
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@ -277,51 +276,48 @@ func el2_sysregs_context_restore
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msr esr_el2, x14
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msr far_el2, x15
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ldp x16, x17, [x0, #CTX_FPEXC32_EL2]
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msr fpexc32_el2, x16
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msr hacr_el2, x17
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ldp x16, x17, [x0, #CTX_HACR_EL2]
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msr hacr_el2, x16
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msr hcr_el2, x17
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ldp x9, x10, [x0, #CTX_HCR_EL2]
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msr hcr_el2, x9
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msr hpfar_el2, x10
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ldp x9, x10, [x0, #CTX_HPFAR_EL2]
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msr hpfar_el2, x9
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msr hstr_el2, x10
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ldp x11, x12, [x0, #CTX_HSTR_EL2]
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msr hstr_el2, x11
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msr ICC_SRE_EL2, x12
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ldp x11, x12, [x0, #CTX_ICC_SRE_EL2]
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msr ICC_SRE_EL2, x11
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msr ICH_HCR_EL2, x12
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ldp x13, x14, [x0, #CTX_ICH_HCR_EL2]
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msr ICH_HCR_EL2, x13
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msr ICH_VMCR_EL2, x14
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ldp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
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msr ICH_VMCR_EL2, x13
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msr mair_el2, x14
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ldp x15, x16, [x0, #CTX_MAIR_EL2]
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msr mair_el2, x15
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msr mdcr_el2, x16
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ldp x15, x16, [x0, #CTX_MDCR_EL2]
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msr mdcr_el2, x15
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msr PMSCR_EL2, x16
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ldr x17, [x0, #CTX_PMSCR_EL2]
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msr PMSCR_EL2, x17
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ldp x17, x9, [x0, #CTX_SPSR_EL2]
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msr spsr_el2, x17
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msr sp_el2, x9
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ldp x10, x11, [x0, #CTX_SPSR_EL2]
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msr spsr_el2, x10
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msr sp_el2, x11
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ldp x10, x11, [x0, #CTX_TPIDR_EL2]
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msr tpidr_el2, x10
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msr ttbr0_el2, x11
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ldr x12, [x0, #CTX_TPIDR_EL2]
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msr tpidr_el2, x12
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ldp x12, x13, [x0, #CTX_VBAR_EL2]
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msr vbar_el2, x12
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msr vmpidr_el2, x13
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ldp x14, x15, [x0, #CTX_TTBR0_EL2]
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msr ttbr0_el2, x14
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msr vbar_el2, x15
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ldp x14, x15, [x0, #CTX_VPIDR_EL2]
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msr vpidr_el2, x14
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msr vtcr_el2, x15
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ldp x16, x17, [x0, #CTX_VMPIDR_EL2]
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msr vmpidr_el2, x16
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msr vpidr_el2, x17
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ldp x9, x10, [x0, #CTX_VTCR_EL2]
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msr vtcr_el2, x9
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msr vttbr_el2, x10
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ldr x16, [x0, #CTX_VTTBR_EL2]
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msr vttbr_el2, x16
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#if CTX_INCLUDE_MTE_REGS
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ldr x11, [x0, #CTX_TFSR_EL2]
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msr TFSR_EL2, x11
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ldr x17, [x0, #CTX_TFSR_EL2]
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msr TFSR_EL2, x17
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#endif
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#if ENABLE_MPAM_FOR_LOWER_ELS
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