From f1be00da0b0acf90355558e01d5f8e1f79c0d481 Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 24 Jan 2020 13:30:28 +0000 Subject: [PATCH] Use correct type when reading SCR register The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt --- bl31/interrupt_mgmt.c | 20 ++++++++++---------- drivers/arm/gic/v3/gicv3_main.c | 6 +++--- include/bl31/interrupt_mgmt.h | 4 ++-- include/lib/el3_runtime/context_mgmt.h | 4 ++-- lib/el3_runtime/aarch64/context_mgmt.c | 22 +++++++++++----------- plat/arm/common/arm_common.c | 4 ++-- plat/mediatek/mt8173/plat_pm.c | 4 ++-- plat/mediatek/mt8183/plat_pm.c | 4 ++-- plat/renesas/rcar/plat_pm.c | 4 ++-- plat/rockchip/common/plat_pm.c | 4 ++-- plat/socionext/synquacer/sq_psci.c | 4 ++-- plat/ti/k3/common/k3_psci.c | 4 ++-- 12 files changed, 42 insertions(+), 42 deletions(-) diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c index e6efad3e0..b8cc3de08 100644 --- a/bl31/interrupt_mgmt.c +++ b/bl31/interrupt_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,11 @@ * registered interrupt handlers for each interrupt type. * The field descriptions are: * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + * * 'flags' : Bit[0], Routing model for this interrupt type when execution is * not in EL3 in the secure state. '1' implies that this * interrupt will be routed to EL3. '0' implies that this @@ -28,16 +33,11 @@ * interrupt will be routed to the current exception level. * * All other bits are reserved and SBZ. - * - * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the - * value of the SCR_EL3.IRQ or FIQ bit for each security state. - * There are two instances of this field corresponding to the - * two security states. ******************************************************************************/ typedef struct intr_type_desc { interrupt_type_handler_t handler; + u_register_t scr_el3[2]; uint32_t flags; - uint32_t scr_el3[2]; } intr_type_desc_t; static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; @@ -78,9 +78,9 @@ static int32_t validate_routing_model(uint32_t type, uint32_t flags) * routing model (expressed through the IRQ and FIQ bits) for a security state * which was stored through a call to 'set_routing_model()' earlier. ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +u_register_t get_scr_el3_from_routing_model(uint32_t security_state) { - uint32_t scr_el3; + u_register_t scr_el3; assert(sec_state_is_valid(security_state)); scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; @@ -103,7 +103,7 @@ static void set_scr_el3_from_rm(uint32_t type, flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); bit_pos = plat_interrupt_type_to_line(type, security_state); - intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos; /* * Update scr_el3 only if there is a context available. If not, it diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index fb49a579d..a672b18f3 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -235,7 +235,7 @@ void gicv3_rdistif_on(unsigned int proc_num) void gicv3_cpuif_enable(unsigned int proc_num) { uintptr_t gicr_base; - unsigned int scr_el3; + u_register_t scr_el3; unsigned int icc_sre_el3; assert(gicv3_driver_data != NULL); @@ -258,7 +258,7 @@ void gicv3_cpuif_enable(unsigned int proc_num) icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); - scr_el3 = (uint32_t) read_scr_el3(); + scr_el3 = read_scr_el3(); /* * Switch to NS state to write Non secure ICC_SRE_EL1 and diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 8bb1bab24..935bf7766 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -134,7 +134,7 @@ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, /******************************************************************************* * Function & variable prototypes ******************************************************************************/ -uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +u_register_t get_scr_el3_from_routing_model(uint32_t security_state); int32_t set_routing_model(uint32_t type, uint32_t flags); int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler_t handler, diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 7c996d124..17955e3a8 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -45,7 +45,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value); void cm_set_next_eret_context(uint32_t security_state); -uint32_t cm_get_scr_el3(uint32_t security_state); +u_register_t cm_get_scr_el3(uint32_t security_state); /* Inline definitions */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index b7908adec..dc4717abe 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,7 +66,7 @@ void __init cm_init(void) void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { unsigned int security_state; - uint32_t scr_el3; + u_register_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; u_register_t sctlr_elx, actlr_elx; @@ -87,7 +87,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * the required value depending on the state of the SPSR_EL3 and the * Security state and entrypoint attributes of the next EL. */ - scr_el3 = (uint32_t)read_scr(); + scr_el3 = read_scr(); scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | SCR_ST_BIT | SCR_HCE_BIT); /* @@ -326,7 +326,7 @@ void cm_init_my_context(const entry_point_info_t *ep) ******************************************************************************/ void cm_prepare_el3_exit(uint32_t security_state) { - uint32_t sctlr_elx, scr_el3, mdcr_el2; + u_register_t sctlr_elx, scr_el3, mdcr_el2; cpu_context_t *ctx = cm_get_context(security_state); bool el2_unused = false; uint64_t hcr_el2 = 0U; @@ -334,11 +334,11 @@ void cm_prepare_el3_exit(uint32_t security_state) assert(ctx != NULL); if (security_state == NON_SECURE) { - scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), + scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); if ((scr_el3 & SCR_HCE_BIT) != 0U) { /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ - sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), + sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); sctlr_elx &= SCTLR_EE_BIT; sctlr_elx |= SCTLR_EL2_RES1; @@ -618,7 +618,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, { cpu_context_t *ctx; el3_state_t *state; - uint32_t scr_el3; + u_register_t scr_el3; ctx = cm_get_context(security_state); assert(ctx != NULL); @@ -634,9 +634,9 @@ void cm_write_scr_el3_bit(uint32_t security_state, * and set it to its new value. */ state = get_el3state_ctx(ctx); - scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); + scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); scr_el3 &= ~(1U << bit_pos); - scr_el3 |= value << bit_pos; + scr_el3 |= (u_register_t)value << bit_pos; write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } @@ -644,7 +644,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the * given security state. ******************************************************************************/ -uint32_t cm_get_scr_el3(uint32_t security_state) +u_register_t cm_get_scr_el3(uint32_t security_state) { cpu_context_t *ctx; el3_state_t *state; @@ -654,7 +654,7 @@ uint32_t cm_get_scr_el3(uint32_t security_state) /* Populate EL3 state so that ERET jumps to the correct entry */ state = get_el3state_ctx(ctx); - return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); + return read_ctx_reg(state, CTX_SCR_EL3); } /******************************************************************************* diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 03d842a51..255e6b421 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -173,7 +173,7 @@ unsigned int plat_get_syscnt_freq2(void) int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) { uint64_t par, pa; - uint32_t scr_el3; + u_register_t scr_el3; /* Doing Non-secure address translation requires SCR_EL3.NS set */ scr_el3 = read_scr_el3(); diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c index c8d45993f..67f1c731b 100644 --- a/plat/mediatek/mt8173/plat_pm.c +++ b/plat/mediatek/mt8173/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -236,7 +236,7 @@ static void mt_platform_restore_context(unsigned long mpidr) static void plat_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); write_scr_el3(scr | SCR_IRQ_BIT); diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c index 2358ec6c4..6094a17be 100644 --- a/plat/mediatek/mt8183/plat_pm.c +++ b/plat/mediatek/mt8183/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * Copyright (c) 2019-2020, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,7 +197,7 @@ static void plat_cluster_pwron_common(uint64_t mpidr, int cluster) static void plat_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c index e678da5dc..6fc47b95c 100644 --- a/plat/renesas/rcar/plat_pm.c +++ b/plat/renesas/rcar/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,7 +56,7 @@ static void rcar_program_mailbox(uint64_t mpidr, uint64_t address) static void rcar_cpu_standby(plat_local_state_t cpu_state) { - uint32_t scr_el3 = read_scr_el3(); + u_register_t scr_el3 = read_scr_el3(); write_scr_el3(scr_el3 | SCR_IRQ_BIT); dsb(); diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c index c9563c9ed..69268870d 100644 --- a/plat/rockchip/common/plat_pm.c +++ b/plat/rockchip/common/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -182,7 +182,7 @@ void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state) ******************************************************************************/ void rockchip_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; assert(cpu_state == PLAT_MAX_RET_STATE); diff --git a/plat/socionext/synquacer/sq_psci.c b/plat/socionext/synquacer/sq_psci.c index 731b19a32..0c97fcf79 100644 --- a/plat/socionext/synquacer/sq_psci.c +++ b/plat/socionext/synquacer/sq_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -155,7 +155,7 @@ void __dead2 sq_system_reset(void) void sq_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; assert(cpu_state == SQ_LOCAL_STATE_RET); diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index de9cefe5b..58588b055 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,7 +21,7 @@ uintptr_t k3_sec_entrypoint; static void k3_cpu_standby(plat_local_state_t cpu_state) { - unsigned int scr; + u_register_t scr; scr = read_scr_el3(); /* Enable the Non secure interrupt to wake the CPU */