diff --git a/changelog.yaml b/changelog.yaml
index c4ed59b9e..9a4a8a7a8 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -113,6 +113,9 @@ subsections:
       - title: Self-hosted Trace Extensions (FEAT_TRF)
         scope: trf
 
+      - title: Statistical profiling Extension (FEAT_SPE)
+        scope: spe
+
   - title: Platforms
 
     subsections:
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index f0d734223..d747efcd7 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -54,9 +54,14 @@ void spe_enable(bool el2_unused)
 	 * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
 	 * and disabled in secure state. Accesses to SPE registers at
 	 * S-EL1 generate trap exceptions to EL3.
+	 *
+	 * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
+	 * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
+	 * Setting this bit to 1 doesn't have any effect on it when
+	 * FEAT_SPEv1p2 not implemented.
 	 */
 	v = read_mdcr_el3();
-	v |= MDCR_NSPB(MDCR_NSPB_EL1);
+	v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
 	write_mdcr_el3(v);
 }