rockchip: plat_pm.c: Change callbacks implement for our SOCs.
Remove struct rockchip_pm_ops_cb and instead of using weak functions implement; in this way we want the codes look clear and simple; Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
This commit is contained in:
parent
bcc2bf0977
commit
f32ab4445a
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@ -45,27 +45,6 @@
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extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
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extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
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/******************************************************************************
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* For rockchip socs pm ops
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******************************************************************************/
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struct rockchip_pm_ops_cb {
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int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint);
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int (*cores_pwr_dm_off)(void);
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int (*cores_pwr_dm_on_finish)(void);
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int (*cores_pwr_dm_suspend)(void);
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int (*cores_pwr_dm_resume)(void);
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/* hlvl is used for clusters or system level */
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int (*hlvl_pwr_dm_suspend)(uint32_t lvl, plat_local_state_t lvl_state);
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int (*hlvl_pwr_dm_resume)(uint32_t lvl, plat_local_state_t lvl_state);
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int (*hlvl_pwr_dm_off)(uint32_t lvl, plat_local_state_t lvl_state);
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int (*hlvl_pwr_dm_on_finish)(uint32_t lvl,
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plat_local_state_t lvl_state);
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int (*sys_pwr_dm_suspend)(void);
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int (*sys_pwr_dm_resume)(void);
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void (*sys_gbl_soft_reset)(void) __dead2;
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void (*system_off)(void) __dead2;
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void (*sys_pwr_down_wfi)(const psci_power_state_t *state_info) __dead2;
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};
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/******************************************************************************
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* The register have write-mask bits, it is mean, if you want to set the bits,
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@ -120,7 +99,6 @@ void plat_rockchip_gic_pcpu_init(void);
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void plat_rockchip_pmusram_prepare(void);
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void plat_rockchip_pmu_init(void);
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void plat_rockchip_soc_init(void);
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void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops);
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uintptr_t plat_get_sec_entrypoint(void);
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void platform_cpu_warmboot(void);
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@ -131,6 +109,28 @@ struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
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struct apio_info *plat_get_rockchip_suspend_apio(void);
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void plat_rockchip_gpio_init(void);
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint);
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_off(void);
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int rockchip_soc_sys_pwr_dm_suspend(void);
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int rockchip_soc_cores_pwr_dm_suspend(void);
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int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_on_finish(void);
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int rockchip_soc_sys_pwr_dm_resume(void);
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int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
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plat_local_state_t lvl_state);
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int rockchip_soc_cores_pwr_dm_resume(void);
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void __dead2 rockchip_soc_soft_reset(void);
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void __dead2 rockchip_soc_system_off(void);
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void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
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const psci_power_state_t *target_state);
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void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void);
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extern const unsigned char rockchip_power_domain_tree_desc[];
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extern void *pmu_cpuson_entrypoint_start;
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@ -48,7 +48,103 @@
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static uintptr_t rockchip_sec_entrypoint;
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static struct rockchip_pm_ops_cb *rockchip_ops;
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#pragma weak rockchip_soc_cores_pwr_dm_on
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#pragma weak rockchip_soc_hlvl_pwr_dm_off
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#pragma weak rockchip_soc_cores_pwr_dm_off
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#pragma weak rockchip_soc_sys_pwr_dm_suspend
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#pragma weak rockchip_soc_cores_pwr_dm_suspend
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#pragma weak rockchip_soc_hlvl_pwr_dm_suspend
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#pragma weak rockchip_soc_hlvl_pwr_dm_on_finish
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#pragma weak rockchip_soc_cores_pwr_dm_on_finish
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#pragma weak rockchip_soc_sys_pwr_dm_resume
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#pragma weak rockchip_soc_hlvl_pwr_dm_resume
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#pragma weak rockchip_soc_cores_pwr_dm_resume
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#pragma weak rockchip_soc_soft_reset
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#pragma weak rockchip_soc_system_off
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#pragma weak rockchip_soc_sys_pd_pwr_dn_wfi
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#pragma weak rockchip_soc_cores_pd_pwr_dn_wfi
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_off(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_sys_pwr_dm_suspend(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_suspend(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_on_finish(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_sys_pwr_dm_resume(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_resume(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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void __dead2 rockchip_soc_soft_reset(void)
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{
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while (1)
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;
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}
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void __dead2 rockchip_soc_system_off(void)
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{
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while (1)
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;
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}
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void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
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const psci_power_state_t *target_state)
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{
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psci_power_down_wfi();
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}
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void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
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{
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psci_power_down_wfi();
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}
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/*******************************************************************************
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* Rockchip standard platform handler called to check the validity of the power
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@ -131,10 +227,7 @@ void rockchip_cpu_standby(plat_local_state_t cpu_state)
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******************************************************************************/
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int rockchip_pwr_domain_on(u_register_t mpidr)
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{
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if (rockchip_ops && rockchip_ops->cores_pwr_dm_on)
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rockchip_ops->cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint);
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return PSCI_E_SUCCESS;
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return rockchip_soc_cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint);
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}
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/*******************************************************************************
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@ -145,6 +238,7 @@ void rockchip_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
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@ -153,17 +247,13 @@ void rockchip_pwr_domain_off(const psci_power_state_t *target_state)
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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plat_cci_disable();
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if (!rockchip_ops || !rockchip_ops->cores_pwr_dm_off)
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return;
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rockchip_ops->cores_pwr_dm_off();
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if (!rockchip_ops->hlvl_pwr_dm_off)
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return;
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rockchip_soc_cores_pwr_dm_off();
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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rockchip_ops->hlvl_pwr_dm_off(lvl, lvl_state);
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ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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}
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@ -175,18 +265,15 @@ void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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if (rockchip_ops) {
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE &&
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rockchip_ops->sys_pwr_dm_suspend) {
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rockchip_ops->sys_pwr_dm_suspend();
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} else if (rockchip_ops->cores_pwr_dm_suspend) {
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rockchip_ops->cores_pwr_dm_suspend();
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}
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}
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rockchip_soc_sys_pwr_dm_suspend();
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else
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rockchip_soc_cores_pwr_dm_suspend();
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/* Prevent interrupts from spuriously waking up this cpu */
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plat_rockchip_gic_cpuif_disable();
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@ -198,12 +285,11 @@ void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state)
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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return;
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if (!rockchip_ops || !rockchip_ops->hlvl_pwr_dm_suspend)
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return;
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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rockchip_ops->hlvl_pwr_dm_suspend(lvl, lvl_state);
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ret = rockchip_soc_hlvl_pwr_dm_suspend(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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}
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@ -216,22 +302,18 @@ void rockchip_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
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if (!rockchip_ops)
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goto comm_finish;
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if (rockchip_ops->hlvl_pwr_dm_on_finish) {
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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rockchip_ops->hlvl_pwr_dm_on_finish(lvl, lvl_state);
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}
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_on_finish(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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if (rockchip_ops->cores_pwr_dm_on_finish)
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rockchip_ops->cores_pwr_dm_on_finish();
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comm_finish:
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rockchip_soc_cores_pwr_dm_on_finish();
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/* Perform the common cluster specific operations */
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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@ -257,34 +339,30 @@ void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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/* Nothing to be done on waking up from retention from CPU level */
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if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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/* Perform system domain restore if woken up from system suspend */
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if (!rockchip_ops)
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goto comm_finish;
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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if (rockchip_ops->sys_pwr_dm_resume)
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rockchip_ops->sys_pwr_dm_resume();
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rockchip_soc_sys_pwr_dm_resume();
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goto comm_finish;
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}
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if (rockchip_ops->hlvl_pwr_dm_resume) {
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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rockchip_ops->hlvl_pwr_dm_resume(lvl, lvl_state);
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}
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_resume(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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if (rockchip_ops->cores_pwr_dm_resume)
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rockchip_ops->cores_pwr_dm_resume();
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rockchip_soc_cores_pwr_dm_resume();
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/*
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* Program the gic per-cpu distributor or re-distributor interface.
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* For sys power domain operation, resuming of the gic needs to operate
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* in rockchip_ops->sys_pwr_dm_resume, according to the sys power mode
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* in rockchip_soc_sys_pwr_dm_resume(), according to the sys power mode
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* implements.
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*/
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plat_rockchip_gic_cpuif_enable();
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@ -302,9 +380,7 @@ comm_finish:
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******************************************************************************/
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static void __dead2 rockchip_system_reset(void)
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{
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assert(rockchip_ops && rockchip_ops->sys_gbl_soft_reset);
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rockchip_ops->sys_gbl_soft_reset();
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rockchip_soc_soft_reset();
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}
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/*******************************************************************************
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@ -312,9 +388,16 @@ static void __dead2 rockchip_system_reset(void)
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******************************************************************************/
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static void __dead2 rockchip_system_poweroff(void)
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{
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assert(rockchip_ops && rockchip_ops->system_off);
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rockchip_soc_system_off();
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}
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rockchip_ops->system_off();
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static void __dead2 rockchip_pd_pwr_down_wfi(
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const psci_power_state_t *target_state)
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{
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rockchip_soc_sys_pd_pwr_dn_wfi();
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else
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rockchip_soc_cores_pd_pwr_dn_wfi(target_state);
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}
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/*******************************************************************************
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@ -348,8 +431,3 @@ uintptr_t plat_get_sec_entrypoint(void)
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assert(rockchip_sec_entrypoint);
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return rockchip_sec_entrypoint;
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}
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void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops)
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{
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rockchip_ops = ops;
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}
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@ -623,7 +623,7 @@ static void nonboot_cpus_off(void)
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}
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}
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static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
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{
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uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
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@ -635,19 +635,20 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
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cpus_power_domain_on(cpu_id);
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return 0;
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return PSCI_E_SUCCESS;
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}
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static int cores_pwr_domain_off(void)
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int rockchip_soc_cores_pwr_dm_off(void)
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{
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uint32_t cpu_id = plat_my_core_pos();
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cpus_power_domain_off(cpu_id, core_pwr_wfi);
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return 0;
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return PSCI_E_SUCCESS;
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}
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static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state)
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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switch (lvl) {
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case MPIDR_AFFLVL1:
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@ -657,10 +658,10 @@ static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state)
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break;
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}
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return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int cores_pwr_domain_suspend(void)
|
||||
int rockchip_soc_cores_pwr_dm_suspend(void)
|
||||
{
|
||||
uint32_t cpu_id = plat_my_core_pos();
|
||||
|
||||
|
@ -672,10 +673,10 @@ static int cores_pwr_domain_suspend(void)
|
|||
|
||||
cpus_power_domain_off(cpu_id, core_pwr_wfi_int);
|
||||
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state)
|
||||
int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
|
||||
{
|
||||
switch (lvl) {
|
||||
case MPIDR_AFFLVL1:
|
||||
|
@ -685,20 +686,20 @@ static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state)
|
|||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int cores_pwr_domain_on_finish(void)
|
||||
int rockchip_soc_cores_pwr_dm_on_finish(void)
|
||||
{
|
||||
uint32_t cpu_id = plat_my_core_pos();
|
||||
|
||||
mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
|
||||
CORES_PM_DISABLE);
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int hlvl_pwr_domain_on_finish(uint32_t lvl,
|
||||
plat_local_state_t lvl_state)
|
||||
int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
|
||||
plat_local_state_t lvl_state)
|
||||
{
|
||||
switch (lvl) {
|
||||
case MPIDR_AFFLVL1:
|
||||
|
@ -708,20 +709,20 @@ static int hlvl_pwr_domain_on_finish(uint32_t lvl,
|
|||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int cores_pwr_domain_resume(void)
|
||||
int rockchip_soc_cores_pwr_dm_resume(void)
|
||||
{
|
||||
uint32_t cpu_id = plat_my_core_pos();
|
||||
|
||||
/* Disable core_pm */
|
||||
mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);
|
||||
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state)
|
||||
int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
|
||||
{
|
||||
switch (lvl) {
|
||||
case MPIDR_AFFLVL1:
|
||||
|
@ -730,7 +731,7 @@ static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state)
|
|||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1097,7 +1098,7 @@ static void m0_reset(void)
|
|||
BITS_WITH_WMASK(0x2f, 0x2f, 0));
|
||||
}
|
||||
|
||||
static int sys_pwr_domain_suspend(void)
|
||||
int rockchip_soc_sys_pwr_dm_suspend(void)
|
||||
{
|
||||
uint32_t wait_cnt = 0;
|
||||
uint32_t status = 0;
|
||||
|
@ -1160,7 +1161,7 @@ static int sys_pwr_domain_suspend(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sys_pwr_domain_resume(void)
|
||||
int rockchip_soc_sys_pwr_dm_resume(void)
|
||||
{
|
||||
uint32_t wait_cnt = 0;
|
||||
uint32_t status = 0;
|
||||
|
@ -1247,7 +1248,7 @@ static int sys_pwr_domain_resume(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void __dead2 soc_soft_reset(void)
|
||||
void __dead2 rockchip_soc_soft_reset(void)
|
||||
{
|
||||
struct gpio_info *rst_gpio;
|
||||
|
||||
|
@ -1264,7 +1265,7 @@ void __dead2 soc_soft_reset(void)
|
|||
;
|
||||
}
|
||||
|
||||
void __dead2 soc_system_off(void)
|
||||
void __dead2 rockchip_soc_system_off(void)
|
||||
{
|
||||
struct gpio_info *poweroff_gpio;
|
||||
|
||||
|
@ -1289,28 +1290,11 @@ void __dead2 soc_system_off(void)
|
|||
;
|
||||
}
|
||||
|
||||
static struct rockchip_pm_ops_cb pm_ops = {
|
||||
.cores_pwr_dm_on = cores_pwr_domain_on,
|
||||
.cores_pwr_dm_off = cores_pwr_domain_off,
|
||||
.cores_pwr_dm_on_finish = cores_pwr_domain_on_finish,
|
||||
.cores_pwr_dm_suspend = cores_pwr_domain_suspend,
|
||||
.cores_pwr_dm_resume = cores_pwr_domain_resume,
|
||||
.hlvl_pwr_dm_suspend = hlvl_pwr_domain_suspend,
|
||||
.hlvl_pwr_dm_resume = hlvl_pwr_domain_resume,
|
||||
.hlvl_pwr_dm_off = hlvl_pwr_domain_off,
|
||||
.hlvl_pwr_dm_on_finish = hlvl_pwr_domain_on_finish,
|
||||
.sys_pwr_dm_suspend = sys_pwr_domain_suspend,
|
||||
.sys_pwr_dm_resume = sys_pwr_domain_resume,
|
||||
.sys_gbl_soft_reset = soc_soft_reset,
|
||||
.system_off = soc_system_off,
|
||||
};
|
||||
|
||||
void plat_rockchip_pmu_init(void)
|
||||
{
|
||||
uint32_t cpu;
|
||||
|
||||
rockchip_pd_lock_init();
|
||||
plat_setup_rockchip_pm_ops(&pm_ops);
|
||||
|
||||
/* register requires 32bits mode, switch it to 32 bits */
|
||||
cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot;
|
||||
|
|
Loading…
Reference in New Issue