Tegra194: memctrl: platform handlers to reprogram MSS
Introduce platform handlers to reprogram the MSS settings. Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
1e6a7f9179
commit
f32e852596
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@ -50,45 +50,6 @@
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#define BOARD_SHIFT_BITS 24U
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#define MISCREG_PFCFG 0x200CU
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/*******************************************************************************
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* Tegra TSA Controller constants
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******************************************************************************/
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#define TEGRA_TSA_BASE 0x02000000
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#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010
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#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034
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#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008
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#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008
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#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008
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#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008
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#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038
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#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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@ -137,7 +98,6 @@
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#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
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/* Memory Controller Reset Control registers */
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#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27)
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#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28)
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#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29)
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#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30)
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@ -228,143 +188,6 @@
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#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
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#define GPU_RESET_BIT (1UL << 0)
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/*******************************************************************************
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* Stream ID Override Config registers
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******************************************************************************/
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#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
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#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
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#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
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#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
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#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
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#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
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#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
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#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
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#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
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#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
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#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
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#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U
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#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U
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#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U
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#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U
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#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
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#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
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#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
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#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
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#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
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#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
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#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
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#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
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#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U
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#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U
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#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U
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#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
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#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
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#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
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#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
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#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
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#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
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#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
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#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
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#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
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#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U
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#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U
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#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U
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/*******************************************************************************
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* Memory Controller transaction override config registers
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******************************************************************************/
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#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530
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#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538
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#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540
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#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548
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#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570
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#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578
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#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580
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#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C
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#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4
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#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC
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#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4
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#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC
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#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604
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#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C
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#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614
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#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C
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#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624
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#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C
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#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634
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#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C
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#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644
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#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C
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#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654
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#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C
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#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664
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#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C
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#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674
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#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C
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#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684
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#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C
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#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694
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#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C
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#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4
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#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC
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#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4
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#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC
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#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4
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#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC
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#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4
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#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC
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#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4
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#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC
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#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4
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#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC
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#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704
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#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C
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#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714
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#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C
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#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724
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#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C
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#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754
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#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C
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#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764
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#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C
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#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774
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#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C
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#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784
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#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C
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#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794
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#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C
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#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC
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#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4
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#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC
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/*******************************************************************************
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* XUSB PADCTL
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******************************************************************************/
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@ -4,8 +4,12 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <assert.h>
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#include <common/bl_common.h>
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#include <mce.h>
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#include <memctrl_v2.h>
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#include <tegra_mc_def.h>
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#include <tegra_platform.h>
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/*******************************************************************************
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* Array to hold stream_id override config register offsets
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@ -297,6 +301,325 @@ const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = {
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mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
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};
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/* To be called by common memctrl_v2.c */
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static void tegra194_memctrl_reconfig_mss_clients(void)
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{
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uint32_t reg_val, wdata_0, wdata_1, wdata_2;
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((reg_val & wdata_0) != wdata_0);
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wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
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MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((reg_val & wdata_1) != wdata_1);
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wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
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if (tegra_platform_is_silicon()) {
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wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
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}
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
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} while ((reg_val & wdata_2) != wdata_2);
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/*
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* Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
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* strongly ordered MSS clients.
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*
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* MC clients with default SO_DEV override still enabled at TSA:
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* EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
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* PCIe3w, PCIe4w and PCIe5w.
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*/
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mc_set_tsa_w_passthrough(AONDMAW);
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mc_set_tsa_w_passthrough(AONW);
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mc_set_tsa_w_passthrough(APEDMAW);
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mc_set_tsa_w_passthrough(APEW);
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mc_set_tsa_w_passthrough(AXISW);
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mc_set_tsa_w_passthrough(BPMPDMAW);
|
||||
mc_set_tsa_w_passthrough(BPMPW);
|
||||
mc_set_tsa_w_passthrough(ETRW);
|
||||
mc_set_tsa_w_passthrough(SCEDMAW);
|
||||
mc_set_tsa_w_passthrough(RCEDMAW);
|
||||
mc_set_tsa_w_passthrough(RCEW);
|
||||
mc_set_tsa_w_passthrough(SDMMCW);
|
||||
mc_set_tsa_w_passthrough(SDMMCWA);
|
||||
mc_set_tsa_w_passthrough(SDMMCWAB);
|
||||
mc_set_tsa_w_passthrough(SESWR);
|
||||
mc_set_tsa_w_passthrough(TSECSWR);
|
||||
mc_set_tsa_w_passthrough(TSECSWRB);
|
||||
mc_set_tsa_w_passthrough(UFSHCW);
|
||||
mc_set_tsa_w_passthrough(VICSWR);
|
||||
mc_set_tsa_w_passthrough(VIFALW);
|
||||
|
||||
/* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
|
||||
* ISO clients(DISP, VI, EQOS) should never snoop caches and
|
||||
* don't need ROC/PCFIFO ordering.
|
||||
* ISO clients(EQOS) that need ordering should use PCFIFO ordering
|
||||
* and bypass ROC ordering by using FORCE_NON_COHERENT path.
|
||||
* FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
|
||||
* over SMMU attributes.
|
||||
* Force all Normal memory transactions from ISO and non-ISO to be
|
||||
* non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
|
||||
* Force the SO_DEV transactions from ordered ISO clients(EQOS) to
|
||||
* non-coherent path and enable MC PCFIFO interlock for ordering.
|
||||
* Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
|
||||
* XUSB, SATA) to coherent so that the transactions are
|
||||
* ordered by ROC.
|
||||
* PCFIFO ensure write ordering.
|
||||
* Read after Write ordering is maintained/enforced by MC clients.
|
||||
* Clients that need PCIe type write ordering must
|
||||
* go through ROC ordering.
|
||||
* Ordering enable for Read clients is not necessary.
|
||||
* R5's and A9 would get necessary ordering from AXI and
|
||||
* don't need ROC ordering enable:
|
||||
* - MMIO ordering is through dev mapping and MMIO
|
||||
* accesses bypass SMMU.
|
||||
* - Normal memory is accessed through SMMU and ordering is
|
||||
* ensured by client and AXI.
|
||||
* - Ack point for Normal memory is WCAM in MC.
|
||||
* - MMIO's can be early acked and AXI ensures dev memory ordering,
|
||||
* Client ensures read/write direction change ordering.
|
||||
* - See Bug 200312466 for more details.
|
||||
*
|
||||
* CGID_TAG_ADR is only present from T186 A02. As this code is common
|
||||
* between A01 and A02, tegra_memctrl_set_overrides() programs
|
||||
* CGID_TAG_ADR for the necessary clients on A02.
|
||||
*/
|
||||
mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
|
||||
FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
|
||||
FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
|
||||
FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
|
||||
FORCE_COHERENT_SNOOP);
|
||||
if (tegra_platform_is_silicon()) {
|
||||
mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
|
||||
mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO,
|
||||
NO_OVERRIDE, NO_OVERRIDE);
|
||||
}
|
||||
/*
|
||||
* At this point, ordering can occur at ROC. So, remove PCFIFO's
|
||||
* control over ordering requests.
|
||||
*
|
||||
* Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
|
||||
* boot and strongly ordered MSS clients
|
||||
*/
|
||||
/* SATAW is ordered client */
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL |
|
||||
mc_set_pcfifo_ordered_boot_so_mss(1, SATAW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
|
||||
/* XUSB_DEVW has PCFIFO enabled. */
|
||||
reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
|
||||
/* EQOSW has PCFIFO order enabled. */
|
||||
reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
|
||||
/* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */
|
||||
reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) |
|
||||
mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) |
|
||||
mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
|
||||
|
||||
reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
|
||||
|
||||
/* Set Order Id only for the clients having non zero order id */
|
||||
reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL &
|
||||
mc_client_order_id(9, XUSB_HOSTW);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
|
||||
|
||||
reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL &
|
||||
mc_client_order_id(27, PCIE0W);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
|
||||
|
||||
reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL &
|
||||
mc_client_order_id(28, PCIE4W) &
|
||||
mc_client_order_id(28, PCIE5W);
|
||||
tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
|
||||
|
||||
/* Set VC Id only for the clients having different reset values */
|
||||
reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL &
|
||||
/*
|
||||
* SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB,
|
||||
* TSECSWR and TSECSWRB clients
|
||||
*/
|
||||
mc_hub_vc_id(0, APB);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
|
||||
|
||||
reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL &
|
||||
/* SDMMCRAB and SDMMCWAB clients */
|
||||
mc_hub_vc_id(2, SD);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
|
||||
|
||||
reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL &
|
||||
/* AXIR and AXIW clients */
|
||||
mc_hub_vc_id(4, NIC);
|
||||
tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
|
||||
|
||||
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
|
||||
|
||||
wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
|
||||
|
||||
wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Struct to hold the memory controller settings
|
||||
******************************************************************************/
|
||||
|
|
@ -306,7 +629,8 @@ static tegra_mc_settings_t tegra194_mc_settings = {
|
|||
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
|
||||
.num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs),
|
||||
.txn_override_cfg = tegra194_txn_override_cfgs,
|
||||
.num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs)
|
||||
.num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs),
|
||||
.reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <mce.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_mc_def.h>
|
||||
#include <tegra_platform.h>
|
||||
#include <tegra_private.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <common/debug.h>
|
||||
#include <smmu.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_mc_def.h>
|
||||
|
||||
#define BOARD_SYSTEM_FPGA_BASE U(1)
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||||
#define BASE_CONFIG_SMMU_DEVICES U(2)
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||||
|
|
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|||
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Reference in New Issue