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poplar: Add BL32 (OP-TEE) support 

Signed-off-by: Victor Chong <victor.chong@linaro.org>
This commit is contained in:
Victor Chong 2017-10-28 01:59:41 +09:00
parent d45a1c303e
commit f336774b45
7 changed files with 139 additions and 3 deletions
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5
plat/hisilicon/poplar/aarch64/platform_common.c
View File

@ -25,9 +25,14 @@
DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
TSP_SEC_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
static const mmap_region_t poplar_mmap[] = {
MAP_DDR,
MAP_DEVICE,
MAP_TSP_MEM,
{0}
};

47
plat/hisilicon/poplar/bl2_plat_setup.c
View File

@ -29,8 +29,10 @@
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
@ -61,6 +63,16 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
PARAM_IMAGE_BINARY, VERSION_1, 0);
/* Fill BL3-2 related information if it exists */
#ifdef BL32_BASE
bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
VERSION_1, 0);
bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
#endif
/* Fill BL3-3 related information */
bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
@ -89,6 +101,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
* Before calling this function BL32 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL32 and set SPSR and security state.
* On Poplar we only set the security state of the entrypoint
******************************************************************************/
#ifdef BL32_BASE
void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
entry_point_info_t *bl32_ep_info)
{
SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL32 image.
*/
bl32_ep_info->spsr = 0;
}
/*******************************************************************************
* Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL32.
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
}
#endif /* BL32_BASE */
static uint32_t hisi_get_spsr_for_bl33_entry(void)
{
unsigned long el_status;

22
plat/hisilicon/poplar/bl31_plat_setup.c
View File

@ -34,6 +34,7 @@
#define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
static void hisi_tzpc_sec_init(void)
@ -43,7 +44,19 @@ static void hisi_tzpc_sec_init(void)
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
return &bl33_image_ep_info;
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
next_image_info = (type == NON_SECURE)
? &bl33_image_ep_info : &bl32_image_ep_info;
/*
* None of the images on the ARM development platforms can have 0x0
* as the entrypoint
*/
if (next_image_info->pc)
return next_image_info;
else
return NULL;
}
void bl31_early_platform_setup(bl31_params_t *from_bl2,
@ -54,6 +67,13 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
/* Init console for crash report */
plat_crash_console_init();
/*
* Copy BL32 (if populated by BL2) and BL33 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
if (from_bl2->bl32_ep_info)
bl32_image_ep_info = *from_bl2->bl32_ep_info;
bl33_image_ep_info = *from_bl2->bl33_ep_info;
}

44
plat/hisilicon/poplar/include/platform_def.h
View File

@ -48,10 +48,54 @@
#define TEE_SEC_MEM_BASE (0x70000000)
#define TEE_SEC_MEM_SIZE (0x10000000)
/* Memory location options for TSP */
#define POPLAR_SRAM_ID 0
#define POPLAR_DRAM_ID 1
/*
* DDR for OP-TEE (28MB from 0x02200000 -0x04000000) is divided in several
* regions:
* - Secure DDR (default is the top 16MB) used by OP-TEE
* - Non-secure DDR (4MB) reserved for OP-TEE's future use
* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
* - Non-secure DDR (2MB) reserved for OP-TEE's future use
*/
#define DDR_SEC_SIZE 0x01000000
#define DDR_SEC_BASE 0x03000000
#define BL_MEM_BASE (BL1_RO_BASE)
#define BL_MEM_LIMIT (BL31_LIMIT)
#define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE)
/*
* BL3-2 specific defines.
*/
/*
* The TSP currently executes from TZC secured area of DRAM.
*/
#define BL32_DRAM_BASE 0x03000000
#define BL32_DRAM_LIMIT 0x04000000
#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
#define BL32_BASE BL32_DRAM_BASE
#define BL32_LIMIT BL32_DRAM_LIMIT
#elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID)
#error "SRAM storage of TSP payload is currently unsupported"
#else
#error "Currently unsupported POPLAR_TSP_LOCATION_ID value"
#endif
/* BL32 is mandatory in AArch32 */
#ifndef AARCH32
#ifdef SPD_none
#undef BL32_BASE
#endif /* SPD_none */
#endif
#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
/* Page table and MMU setup constants */

4
plat/hisilicon/poplar/include/poplar_layout.h
View File

@ -74,9 +74,9 @@
* "OFFSET" is an offset to the start of a region relative to the
* base of the "l-loader" TEXT section (also a multiple of page size).
*/
#define LLOADER_TEXT_BASE 0x00001000 /* page aligned */
#define LLOADER_TEXT_BASE 0x02001000 /* page aligned */
#define BL1_OFFSET 0x0000D000 /* page multiple */
#define FIP_BASE 0x00040000
#define FIP_BASE 0x02040000
#define BL1_RO_SIZE 0x00008000 /* page multiple */
#define BL1_RW_SIZE 0x00008000 /* page multiple */

9
plat/hisilicon/poplar/plat_storage.c
View File

@ -43,6 +43,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
};
static const io_uuid_spec_t bl32_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
@ -69,6 +73,11 @@ static const struct plat_io_policy policies[] = {
(uintptr_t)&bl31_uuid_spec,
open_fip
},
[BL32_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_uuid_spec,
open_fip
},
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,

11
plat/hisilicon/poplar/platform.mk
View File

@ -4,6 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
# On Poplar, the TSP can execute from TZC secure area in DRAM.
POPLAR_TSP_RAM_LOCATION := dram
ifeq (${POPLAR_TSP_RAM_LOCATION}, dram)
POPLAR_TSP_RAM_LOCATION_ID = POPLAR_DRAM_ID
else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
POPLAR_TSP_RAM_LOCATION_ID := POPLAR_SRAM_ID
else
$(error "Currently unsupported POPLAR_TSP_RAM_LOCATION value")
endif
$(eval $(call add_define,POPLAR_TSP_RAM_LOCATION_ID))
NEED_BL33 := yes
COLD_BOOT_SINGLE_CPU := 1