stm32mp1: add general SYSCFG management
The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
8f282dae74
commit
f33b2433f5
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@ -323,6 +323,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
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_CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
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_CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
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_CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
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_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
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_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
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_CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
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@ -146,6 +146,12 @@
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status = "okay";
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};
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&pwr {
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pwr-regulators {
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vdd-supply = <&vdd>;
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};
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};
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&rng1 {
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status = "okay";
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};
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@ -143,6 +143,12 @@
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status = "okay";
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};
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&pwr {
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pwr-regulators {
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vdd-supply = <&vdd>;
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};
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};
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&rng1 {
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status = "okay";
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};
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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@ -170,6 +170,12 @@
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};
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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rng1: rng@54003000 {
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compatible = "st,stm32-rng";
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reg = <0x54003000 0x400>;
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@ -41,6 +41,8 @@ uint32_t dt_get_ddr_size(void);
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uintptr_t dt_get_ddrctrl_base(void);
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uintptr_t dt_get_ddrphyc_base(void);
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uintptr_t dt_get_pwr_base(void);
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uint32_t dt_get_pwr_vdd_voltage(void);
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uintptr_t dt_get_syscfg_base(void);
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const char *dt_get_board_model(void);
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#endif /* STM32MP_DT_H */
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@ -358,6 +358,68 @@ uintptr_t dt_get_pwr_base(void)
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return fdt32_to_cpu(*cuint);
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}
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/*******************************************************************************
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* This function gets PWR VDD regulator voltage information from the DT.
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* Returns value in microvolts on success, and 0 on failure.
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******************************************************************************/
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uint32_t dt_get_pwr_vdd_voltage(void)
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{
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int node, pwr_regulators_node;
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const fdt32_t *cuint;
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node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
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if (node < 0) {
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INFO("%s: Cannot read PWR node in DT\n", __func__);
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return 0;
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}
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pwr_regulators_node = fdt_subnode_offset(fdt, node, "pwr-regulators");
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if (node < 0) {
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INFO("%s: Cannot read pwr-regulators node in DT\n", __func__);
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return 0;
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}
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cuint = fdt_getprop(fdt, pwr_regulators_node, "vdd-supply", NULL);
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if (cuint == NULL) {
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return 0;
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}
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node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
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if (node < 0) {
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return 0;
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}
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cuint = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
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if (cuint == NULL) {
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return 0;
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}
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return fdt32_to_cpu(*cuint);
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}
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/*******************************************************************************
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* This function gets SYSCFG base address information from the DT.
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* Returns value on success, and 0 on failure.
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******************************************************************************/
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uintptr_t dt_get_syscfg_base(void)
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{
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int node;
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const fdt32_t *cuint;
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node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT);
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if (node < 0) {
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INFO("%s: Cannot read SYSCFG node in DT\n", __func__);
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return 0;
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}
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cuint = fdt_getprop(fdt, node, "reg", NULL);
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if (cuint == NULL) {
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return 0;
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}
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return fdt32_to_cpu(*cuint);
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}
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/*******************************************************************************
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* This function retrieves board model from DT
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* Returns string taken from model node, NULL otherwise
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@ -15,6 +15,7 @@
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#include <common/desc_image_load.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32mp_pmic.h>
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#include <drivers/st/stm32mp_reset.h>
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@ -211,6 +212,10 @@ void bl2_el3_plat_arch_setup(void)
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;
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}
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if (bsec_probe() != 0) {
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panic();
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}
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/* Reset backup domain on cold boot cases */
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if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
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mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
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@ -236,6 +241,8 @@ void bl2_el3_plat_arch_setup(void)
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panic();
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}
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stm32mp1_syscfg_init();
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result = dt_get_stdout_uart_info(&dt_uart_info);
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if ((result <= 0) ||
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@ -17,4 +17,8 @@ void stm32mp1_security_setup(void);
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void stm32mp1_gic_pcpu_init(void);
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void stm32mp1_gic_init(void);
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void stm32mp1_syscfg_init(void);
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void stm32mp1_syscfg_enable_io_compensation(void);
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void stm32mp1_syscfg_disable_io_compensation(void);
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#endif /* STM32MP1_PRIVATE_H */
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@ -65,7 +65,8 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
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plat/st/common/stm32mp_dt.c \
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plat/st/stm32mp1/stm32mp1_context.c \
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plat/st/stm32mp1/stm32mp1_helper.S \
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plat/st/stm32mp1/stm32mp1_security.c
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plat/st/stm32mp1/stm32mp1_security.c \
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plat/st/stm32mp1/stm32mp1_syscfg.c
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BL2_SOURCES += drivers/io/io_block.c \
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drivers/io/io_dummy.c \
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@ -239,11 +239,15 @@ enum ddr_type {
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/* OTP offsets */
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#define DATA0_OTP U(0)
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#define HW2_OTP U(18)
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/* OTP mask */
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/* DATA0 */
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#define DATA0_OTP_SECURED BIT(6)
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/* HW2 OTP */
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#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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@ -277,5 +281,6 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
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******************************************************************************/
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#define DT_PWR_COMPAT "st,stm32mp1-pwr"
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#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
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#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
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#endif /* STM32MP1_DEF_H */
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@ -0,0 +1,180 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/stpmic1.h>
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#include <lib/mmio.h>
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#include <stm32mp_dt.h>
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#include <stm32mp1_private.h>
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/*
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* SYSCFG REGISTER OFFSET (base relative)
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*/
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#define SYSCFG_BOOTR 0x00U
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#define SYSCFG_IOCTRLSETR 0x18U
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#define SYSCFG_ICNR 0x1CU
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#define SYSCFG_CMPCR 0x20U
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#define SYSCFG_CMPENSETR 0x24U
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/*
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* SYSCFG_BOOTR Register
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*/
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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/*
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* SYSCFG_IOCTRLSETR Register
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*/
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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/*
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* SYSCFG_ICNR Register
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*/
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#define SYSCFG_ICNR_AXI_M9 BIT(9)
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/*
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* SYSCFG_CMPCR Register
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*/
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPCR_RANSRC GENMASK(19, 16)
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#define SYSCFG_CMPCR_RANSRC_SHIFT 16
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#define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
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#define SYSCFG_CMPCR_ANSRC_SHIFT 24
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/*
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* SYSCFG_CMPENSETR Register
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*/
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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void stm32mp1_syscfg_init(void)
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{
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uint32_t bootr;
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uint32_t otp = 0;
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uint32_t vdd_voltage;
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uintptr_t syscfg_base = dt_get_syscfg_base();
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/*
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* Interconnect update : select master using the port 1.
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* LTDC = AXI_M9.
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*/
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mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
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/* Disable Pull-Down for boot pin connected to VDD */
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bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) &
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SYSCFG_BOOTR_BOOT_MASK;
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mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
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bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
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/*
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* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* It could be disabled for low frequencies or if AFMUX is selected
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* but the function is not used, typically for TRACE.
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* If high speed low voltage pad mode is node enable, platform will
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* over consume.
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*
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* WARNING:
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* Enabling High Speed mode while VDD > 2.7V
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* with the OTP product_below_2v5 (OTP 18, BIT 13)
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* erroneously set to 1 can damage the SoC!
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* => TF-A enables the low power mode only if VDD < 2.7V (in DT)
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* but this value needs to be consistent with board design.
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*/
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if (bsec_read_otp(&otp, HW2_OTP) != BSEC_OK) {
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panic();
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}
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otp = otp & HW2_OTP_PRODUCT_BELOW_2V5;
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/* Get VDD supply */
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vdd_voltage = dt_get_pwr_vdd_voltage();
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/* Check if VDD is Low Voltage */
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if (vdd_voltage == 0U) {
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WARN("VDD unknown");
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} else if (vdd_voltage < 2700000U) {
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mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR,
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SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
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SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
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SYSCFG_IOCTRLSETR_HSLVEN_ETH |
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SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
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SYSCFG_IOCTRLSETR_HSLVEN_SPI);
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if (otp == 0U) {
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INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
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}
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} else {
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if (otp != 0U) {
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ERROR("Product_below_2v5=1:\n");
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ERROR("\tHSLVEN update is destructive,\n");
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ERROR("\tno update as VDD > 2.7V\n");
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panic();
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}
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}
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stm32mp1_syscfg_enable_io_compensation();
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}
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void stm32mp1_syscfg_enable_io_compensation(void)
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{
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uintptr_t syscfg_base = dt_get_syscfg_base();
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/*
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* Activate automatic I/O compensation.
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* Warning: need to ensure CSI enabled and ready in clock driver.
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* Enable non-secure clock, we assume non-secure is suspended.
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*/
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stm32mp1_clk_enable_non_secure(SYSCFG);
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mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR,
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SYSCFG_CMPENSETR_MPU_EN);
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while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) &
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SYSCFG_CMPCR_READY) == 0U) {
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;
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}
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
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}
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void stm32mp1_syscfg_disable_io_compensation(void)
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{
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uintptr_t syscfg_base = dt_get_syscfg_base();
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uint32_t value;
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/*
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* Deactivate automatic I/O compensation.
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* Warning: CSI is disabled automatically in STOP if not
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* requested for other usages and always OFF in STANDBY.
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* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
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*/
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value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >>
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SYSCFG_CMPCR_ANSRC_SHIFT;
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR,
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SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
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value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) |
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(value << SYSCFG_CMPCR_RANSRC_SHIFT);
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mmio_write_32(syscfg_base + SYSCFG_CMPCR, value);
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mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
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mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR,
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SYSCFG_CMPENSETR_MPU_EN);
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stm32mp1_clk_disable_non_secure(SYSCFG);
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}
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