nxp lx2160a-aqds: new plat based on soc lx2160a
New NXP platform lx2160a-qds: - Based SoC lx2160a - Board specific tuning for DDR init. - Board specific Flash details. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I500ddbe9e56c4af5f955da6ecbd4ddc5fbe89a12
This commit is contained in:
Pankaj Gupta
parent
eb2b193d75
commit
f359a38224
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <load_img.h>
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#include "plat_common.h"
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_3200 = {
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.cs[0].bnds = U(0x03FF),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFFAA0018),
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.timing_cfg[1] = U(0x646A8844),
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.timing_cfg[2] = U(0x00058022),
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.timing_cfg[3] = U(0x13622100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x07401400),
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.timing_cfg[7] = U(0x3BB00000),
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.timing_cfg[8] = U(0x0944AC00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010C50),
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.sdram_mode[1] = U(0x00280400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x10240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x30C00000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct ddr_cfg_regs static_2900 = {
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.cs[0].bnds = U(0x03FF),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFF990018),
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.timing_cfg[1] = U(0x4F4A4844),
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.timing_cfg[2] = U(0x0005601F),
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.timing_cfg[3] = U(0x125F2100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x07401400),
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.timing_cfg[7] = U(0x3AA00000),
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.timing_cfg[8] = U(0x09449B00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010C50),
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.sdram_mode[1] = U(0x00280400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x10240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x2C2E0000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct ddr_cfg_regs static_2600 = {
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.cs[0].bnds = U(0x03FF),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFF880018),
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.timing_cfg[1] = U(0x2A24F444),
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.timing_cfg[2] = U(0x007141DC),
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.timing_cfg[3] = U(0x125B2100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x06401400),
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.timing_cfg[7] = U(0x28800000),
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.timing_cfg[8] = U(0x07338A00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010A70),
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.sdram_mode[1] = U(0x00200400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x0C240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x279C0000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct dimm_params static_dimm = {
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.rdimm = U(0),
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.primary_sdram_width = U(64),
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.ec_sdram_width = U(8),
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.n_ranks = U(2),
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.device_width = U(8),
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.mirrored_dimm = U(1),
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};
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/* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */
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unsigned long long board_static_ddr(struct ddr_info *priv)
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{
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(void)memcpy(&priv->ddr_reg, &static_2900, sizeof(static_2900));
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(void)memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm));
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priv->conf.cs_on_dimm[0] = 0x3;
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ddr_board_options(priv);
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compute_ddr_phy(priv);
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return ULL(0x400000000);
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}
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#elif defined(CONFIG_DDR_NODIMM)
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/*
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* Sample code to bypass reading SPD. This is a sample, not recommended
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* for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1.
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*/
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const struct dimm_params ddr_raw_timing = {
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.n_ranks = U(2),
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.rank_density = U(4294967296u),
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.capacity = U(8589934592u),
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.primary_sdram_width = U(64),
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.ec_sdram_width = U(8),
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.device_width = U(8),
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.die_density = U(0x4),
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.rdimm = U(0),
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.mirrored_dimm = U(1),
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.n_row_addr = U(15),
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.n_col_addr = U(10),
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.bank_addr_bits = U(0),
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.bank_group_bits = U(2),
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.edc_config = U(2),
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.burst_lengths_bitmask = U(0x0c),
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.tckmin_x_ps = 750,
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.tckmax_ps = 1600,
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.caslat_x = U(0x00FFFC00),
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.taa_ps = 13750,
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.trcd_ps = 13750,
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.trp_ps = 13750,
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.tras_ps = 32000,
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.trc_ps = 457500,
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.twr_ps = 15000,
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.trfc1_ps = 260000,
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.trfc2_ps = 160000,
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.trfc4_ps = 110000,
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.tfaw_ps = 21000,
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.trrds_ps = 3000,
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.trrdl_ps = 4900,
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.tccdl_ps = 5000,
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.refresh_rate_ps = U(7800000),
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};
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int ddr_get_ddr_params(struct dimm_params *pdimm,
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struct ddr_conf *conf)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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conf->dimm_in_use[0] = 1; /* Modify accordingly */
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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/* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
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return 0x5;
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}
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#endif /* CONFIG_DDR_NODIMM */
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int ddr_board_options(struct ddr_info *priv)
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{
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struct memctl_opt *popts = &priv->opt;
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const struct ddr_conf *conf = &priv->conf;
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popts->vref_dimm = U(0x24); /* range 1, 83.4% */
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popts->rtt_override = 0;
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popts->rtt_park = U(240);
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popts->otf_burst_chop_en = 0;
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popts->burst_length = U(DDR_BL8);
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popts->trwt_override = U(1);
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popts->bstopre = U(0); /* auto precharge */
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popts->addr_hash = 1;
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/* Set ODT impedance on PHY side */
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switch (conf->cs_on_dimm[1]) {
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case 0xc: /* Two slots dual rank */
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case 0x4: /* Two slots single rank, not valid for interleaving */
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popts->trwt = U(0xf);
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popts->twrt = U(0x7);
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popts->trrt = U(0x7);
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popts->twwt = U(0x7);
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popts->vref_phy = U(0x6B); /* 83.6% */
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popts->odt = U(60);
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popts->phy_tx_impedance = U(28);
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break;
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case 0: /* One slot used */
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default:
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popts->trwt = U(0x3);
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popts->twrt = U(0x3);
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popts->trrt = U(0x3);
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popts->twwt = U(0x3);
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popts->vref_phy = U(0x60); /* 75% */
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popts->odt = U(48);
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popts->phy_tx_impedance = U(28);
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break;
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}
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return 0;
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}
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#ifdef NXP_WARM_BOOT
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long long init_ddr(uint32_t wrm_bt_flg)
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#else
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long long init_ddr(void)
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#endif
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{
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int spd_addr[] = {0x51U, 0x52U, 0x53U, 0x54U};
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struct ddr_info info;
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struct sysinfo sys;
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long long dram_size;
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zeromem(&sys, sizeof(sys));
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if (get_clocks(&sys) == 1) {
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ERROR("System clocks are not set.\n");
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panic();
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}
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(info));
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/* Set two DDRC. Unused DDRC will be removed automatically. */
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info.num_ctlrs = NUM_OF_DDRC;
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info.spd_addr = spd_addr;
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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info.ddr[1] = (void *)NXP_DDR2_ADDR;
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info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
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info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
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info.clk = get_ddr_freq(&sys, 0);
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info.img_loadr = load_img;
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info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
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if (info.clk == 0) {
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info.clk = get_ddr_freq(&sys, 1);
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}
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info.dimm_on_ctlr = DDRC_NUM_DIMM;
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info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
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#ifdef NXP_WARM_BOOT
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info.warm_boot_flag = DDR_COLD_BOOT;
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if (wrm_bt_flg != 0U) {
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info.warm_boot_flag = DDR_WARM_BOOT;
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} else {
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info.warm_boot_flag = DDR_COLD_BOOT;
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}
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#endif
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dram_size = dram_init(&info
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#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
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, NXP_CCN_HN_F_0_ADDR
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#endif
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);
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if (dram_size < 0) {
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ERROR("DDR init failed.\n");
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}
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return dram_size;
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}
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@ -0,0 +1,105 @@
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_DEF_H
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#define PLAT_DEF_H
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#include <arch.h>
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#include <cortex_a72.h>
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/* Required without TBBR.
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* To include the defines for DDR PHY
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* Images.
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*/
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#include <tbbr_img_def.h>
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#include <policy.h>
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#include <soc.h>
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#if defined(IMAGE_BL31)
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#define LS_SYS_TIMCTL_BASE 0x2890000
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#define PLAT_LS_NSTIMER_FRAME_ID 0
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#define LS_CONFIG_CNTACR 1
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#endif
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#define NXP_SYSCLK_FREQ 100000000
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#define NXP_DDRCLK_FREQ 100000000
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/* UART related definition */
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#define NXP_CONSOLE_ADDR NXP_UART_ADDR
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#define NXP_CONSOLE_BAUDRATE 115200
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL2)
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#if defined(TRUSTED_BOARD_BOOT)
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#define PLATFORM_STACK_SIZE 0x2000
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* SD block buffer */
|
||||
#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
|
||||
#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
|
||||
- NXP_SD_BLOCK_BUF_SIZE)
|
||||
|
||||
#ifdef SD_BOOT
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
|
||||
- NXP_SD_BLOCK_BUF_SIZE)
|
||||
#else
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
|
||||
#endif
|
||||
|
||||
/* IO defines as needed by IO driver framework */
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
|
||||
|
||||
/*
|
||||
* FIP image defines - Offset at which FIP Image would be present
|
||||
* Image would include Bl31 , Bl33 and Bl32 (optional)
|
||||
*/
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#define MAX_FIP_DEVICES 3
|
||||
#endif
|
||||
|
||||
#ifndef MAX_FIP_DEVICES
|
||||
#define MAX_FIP_DEVICES 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ID of the secure physical generic timer interrupt used by the BL32.
|
||||
*/
|
||||
#define BL32_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define BL31_WDOG_SEC 89
|
||||
|
||||
#define BL31_NS_WDOG_WS1 108
|
||||
|
||||
/*
|
||||
* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_LS_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
|
||||
#define NXP_IRQ_SEC_SGI_7 15
|
||||
|
||||
#define PLAT_LS_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
#endif
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
#pragma weak board_enable_povdd
|
||||
#pragma weak board_disable_povdd
|
||||
|
||||
bool board_enable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool board_disable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#
|
||||
# Copyright 2018-2020 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# board-specific build parameters
|
||||
|
||||
BOOT_MODE ?= flexspi_nor
|
||||
BOARD ?= lx2160aqds
|
||||
POVDD_ENABLE := no
|
||||
NXP_COINED_BB := no
|
||||
|
||||
# DDR Compilation Configs
|
||||
NUM_OF_DDRC := 1
|
||||
DDRC_NUM_DIMM := 1
|
||||
DDRC_NUM_CS := 2
|
||||
DDR_ECC_EN := yes
|
||||
#enable address decoding feature
|
||||
DDR_ADDR_DEC := yes
|
||||
APPLY_MAX_CDD := yes
|
||||
|
||||
# DDR Errata
|
||||
ERRATA_DDR_A011396 := 1
|
||||
ERRATA_DDR_A050450 := 1
|
||||
|
||||
# On-Board Flash Details
|
||||
FLASH_TYPE := MT35XU512A
|
||||
XSPI_FLASH_SZ := 0x10000000
|
||||
NXP_XSPI_NOR_UNIT_SIZE := 0x20000
|
||||
BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
|
||||
# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
|
||||
# config is enabled for future use cases.
|
||||
FSPI_ERASE_4K := 0
|
||||
|
||||
# Platform specific features.
|
||||
WARM_BOOT := yes
|
||||
|
||||
# Adding platform specific defines
|
||||
|
||||
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
|
||||
|
||||
ifeq (${POVDD_ENABLE},yes)
|
||||
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
|
||||
endif
|
||||
|
||||
ifneq (${FLASH_TYPE},)
|
||||
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
|
||||
endif
|
||||
|
||||
ifneq (${XSPI_FLASH_SZ},)
|
||||
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
|
||||
endif
|
||||
|
||||
ifneq (${FSPI_ERASE_4K},)
|
||||
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
|
||||
endif
|
||||
|
||||
ifneq (${NUM_OF_DDRC},)
|
||||
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
|
||||
endif
|
||||
|
||||
ifneq (${DDRC_NUM_DIMM},)
|
||||
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
|
||||
endif
|
||||
|
||||
ifneq (${DDRC_NUM_CS},)
|
||||
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
|
||||
endif
|
||||
|
||||
ifeq (${DDR_ADDR_DEC},yes)
|
||||
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
|
||||
endif
|
||||
|
||||
ifeq (${DDR_ECC_EN},yes)
|
||||
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
|
||||
endif
|
||||
|
||||
# Platform can control the base address for non-volatile storage.
|
||||
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
|
||||
|
||||
ifeq (${WARM_BOOT},yes)
|
||||
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
|
||||
endif
|
||||
|
||||
# Adding Platform files build files
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
# Adding SoC build info
|
||||
include plat/nxp/soc-lx2160a/soc.mk
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include "plat_def.h"
|
||||
#include "plat_default_def.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/* Following defines affect the PLATFORM SECURITY POLICY */
|
||||
|
||||
/* set this to 0x0 if the platform is not using/responding to ECC errors
|
||||
* set this to 0x1 if ECC is being used (we have to do some init)
|
||||
*/
|
||||
#define POLICY_USING_ECC 0x0
|
||||
|
||||
/* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
/*
|
||||
* POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
|
||||
* POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
|
||||
* POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
|
||||
*/
|
||||
#define POLICY_PERF_WRIOP 0
|
||||
|
||||
/*
|
||||
* set this to '1' if the debug clocks need to remain enabled during
|
||||
* system entry to low-power (LPM20) - this should only be necessary
|
||||
* for testing and NEVER set for normal production
|
||||
*/
|
||||
#define POLICY_DEBUG_ENABLE 0
|
||||
|
||||
|
||||
#endif /* POLICY_H */
|
||||
Loading…
Reference in New Issue