Tegra186: implement `get_target_pwr_state` handler
This patch implements the `get_target_pwr_state` handler for Tegra186 SoCs. The SoC port uses this handler to find out the cluster/system state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls. The MCE firmware controls the power state of the CPU/CLuster/System, so we query it to get the state and act accordingly. Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
87a1df7361
commit
f3a20c3224
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@ -37,6 +37,7 @@
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#include <debug.h>
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#include <denver.h>
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#include <mce.h>
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#include <platform.h>
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#include <psci.h>
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#include <smmu.h>
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#include <string.h>
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@ -71,12 +72,9 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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if (impl == DENVER_IMPL)
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cpu |= 0x4;
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int cpu = plat_my_core_pos();
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/* save the core wake time (us) */
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wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) &
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TEGRA186_WAKE_TIME_MASK;
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@ -84,10 +82,10 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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case PSTATE_ID_CORE_POWERDN:
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/*
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* Core powerdown request only for afflvl 0
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*/
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/* Core powerdown request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
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break;
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@ -103,20 +101,12 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state;
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unsigned int stateid_afflvl0, stateid_afflvl2;
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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int cpu = plat_my_core_pos();
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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mce_cstate_info_t cstate_info = { 0 };
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uint64_t smmu_ctx_base;
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uint32_t val;
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assert(ctx);
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assert(gp_regs);
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if (impl == DENVER_IMPL)
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cpu |= 0x4;
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/* get the state ID */
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pwr_domain_state = target_state->pwr_domain_state;
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stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
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@ -124,29 +114,14 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA186_STATE_ID_MASK;
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if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) {
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if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
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(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
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/* Program default wake mask */
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, TEGRA186_CORE_WAKE_MASK);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 0);
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/* Prepare for cpu idle */
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
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TEGRA_ARI_CORE_C6, wake_time[cpu], 0);
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} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
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/* Program default wake mask */
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, TEGRA186_CORE_WAKE_MASK);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, 0, 0, 0);
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/* Prepare for cpu powerdn */
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
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TEGRA_ARI_CORE_C7, wake_time[cpu], 0);
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/* Enter CPU idle/powerdown */
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val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
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TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7;
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val,
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wake_time[cpu], 0);
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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@ -170,11 +145,11 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
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/* Prepare for system suspend */
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 1);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
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TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC7);
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cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
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cstate_info.system = TEGRA_ARI_SYSTEM_SC7;
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cstate_info.system_state_force = 1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Loop until system suspend is allowed */
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do {
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@ -187,15 +162,84 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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/* Instruct the MCE to enter system suspend state */
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
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TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
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} else {
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ERROR("%s: Unknown state id\n", __func__);
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return PSCI_E_NOT_SUPPORTED;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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unsigned int ncpu)
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{
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plat_local_state_t target = *states;
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int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1;
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int core_pos = read_mpidr() & MPIDR_CPU_MASK;
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mce_cstate_info_t cstate_info = { 0 };
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/* get the current core's power state */
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target = *(states + core_pos);
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/* CPU suspend */
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if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) {
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/* Program default wake mask */
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cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Check if CCx state is allowed. */
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ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED,
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TEGRA_ARI_CORE_C7, wake_time[cpu], 0);
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if (ret)
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return PSTATE_ID_CORE_POWERDN;
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}
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/* CPU off */
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if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) {
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/* find out the number of ON cpus in the cluster */
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do {
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target = *states++;
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if (target != PLAT_MAX_OFF_STATE)
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cluster_powerdn = 0;
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} while (--ncpu);
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/* Enable cluster powerdn from last CPU in the cluster */
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if (cluster_powerdn) {
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/* Enable CC7 state and turn off wake mask */
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cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Check if CCx state is allowed. */
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ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED,
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TEGRA_ARI_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE,
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0);
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if (ret)
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return PSTATE_ID_CORE_POWERDN;
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} else {
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/* Turn off wake_mask */
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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}
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}
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/* System Suspend */
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if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN))
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return PSTATE_ID_SOC_POWERDN;
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/* default state */
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return PSCI_LOCAL_STATE_RUN;
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}
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int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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const plat_local_state_t *pwr_domain_state =
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@ -244,8 +288,7 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
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int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0];
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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mce_cstate_info_t cstate_info = { 0 };
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/*
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* Reset power state info for CPUs when onlining, we set
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@ -256,11 +299,9 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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*/
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if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
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TEGRA_ARI_CLUSTER_CC1, 0, 0);
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cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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}
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/*
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@ -280,15 +321,15 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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tegra_smmu_init();
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/*
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* Reset power state info for the last core doing SC7 entry and exit,
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* we set deepest power state as CC7 and SC7 for SC7 entry which
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* may not be requested by non-secure SW which controls idle states.
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* Reset power state info for the last core doing SC7
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* entry and exit, we set deepest power state as CC7
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* and SC7 for SC7 entry which may not be requested by
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* non-secure SW which controls idle states.
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*/
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
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TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC1);
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cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
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cstate_info.system = TEGRA_ARI_SYSTEM_SC1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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}
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return PSCI_E_SUCCESS;
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@ -296,33 +337,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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assert(ctx);
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assert(gp_regs);
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/* Turn off wake_mask */
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7,
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0, 0);
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/* Disable Denver's DCO operations */
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if (impl == DENVER_IMPL)
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denver_disable_dco();
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/* Turn off CPU */
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return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
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(void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
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MCE_CORE_SLEEP_TIME_INFINITE, 0);
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return PSCI_E_SUCCESS;
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}
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
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mce_cstate_info_t cstate_info = { 0 };
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uint32_t val;
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if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) {
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@ -333,11 +363,11 @@ __dead2 void tegra_soc_prepare_system_off(void)
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} else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) {
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/* Prepare for quasi power down */
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write_ctx_reg(gp_regs, CTX_GPREG_X4, 1);
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write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
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write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
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(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
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TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8);
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cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
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cstate_info.system = TEGRA_ARI_SYSTEM_SC8;
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cstate_info.system_state_force = 1;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* loop until other CPUs power down */
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do {
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@ -357,6 +387,9 @@ __dead2 void tegra_soc_prepare_system_off(void)
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/* power down core */
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prepare_cpu_pwr_dwn();
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/* flush L1/L2 data caches */
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dcsw_op_all(DCCISW);
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} else {
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ERROR("%s: unsupported power down state (%d)\n", __func__,
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tegra186_system_powerdn_state);
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