TF-A AMU extension: fix detection of group 1 counters.
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov
parent
8ae3a91c39
commit
f3ccf036ec
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@ -562,21 +562,14 @@ behaviour of the ``assert()`` function (for example, to save memory).
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doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
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defined, it defaults to ``LOG_LEVEL``.
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If the platform port uses the Activity Monitor Unit, the following constants
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If the platform port uses the Activity Monitor Unit, the following constant
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may be defined:
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- **PLAT_AMU_GROUP1_COUNTERS_MASK**
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This mask reflects the set of group counters that should be enabled. The
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maximum number of group 1 counters supported by AMUv1 is 16 so the mask
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can be at most 0xffff. If the platform does not define this mask, no group 1
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counters are enabled. If the platform defines this mask, the following
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constant needs to also be defined.
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- **PLAT_AMU_GROUP1_NR_COUNTERS**
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This value is used to allocate an array to save and restore the counters
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specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
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This value should be equal to the highest bit position set in the
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mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
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counters are enabled.
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File : plat_macros.S [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -701,6 +701,16 @@
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#define AMEVTYPER1E p15, 0, c13, c15, 6
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#define AMEVTYPER1F p15, 0, c13, c15, 7
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/* AMCFGR definitions */
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#define AMCFGR_NCG_SHIFT U(28)
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#define AMCFGR_NCG_MASK U(0xf)
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#define AMCFGR_N_SHIFT U(0)
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#define AMCFGR_N_MASK U(0xff)
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/* AMCGCR definitions */
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#define AMCGCR_CG1NC_SHIFT U(8)
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#define AMCGCR_CG1NC_MASK U(0xff)
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/*******************************************************************************
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* Definitions for DynamicIQ Shared Unit registers
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******************************************************************************/
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@ -300,11 +300,16 @@ DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
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DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
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DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
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/* Coproc registers for 32bit AMU support */
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DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR)
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DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR)
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DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
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DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
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DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0)
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DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1)
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/* Coproc registers for 64bit AMU support */
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DEFINE_COPROCR_RW_FUNCS_64(amevcntr00, AMEVCNTR00)
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DEFINE_COPROCR_RW_FUNCS_64(amevcntr01, AMEVCNTR01)
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DEFINE_COPROCR_RW_FUNCS_64(amevcntr02, AMEVCNTR02)
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@ -898,9 +898,14 @@
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#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
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#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
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/* AMCFGR_EL0 definitions */
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#define AMCFGR_EL0_NCG_SHIFT U(28)
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#define AMCFGR_EL0_NCG_MASK U(0xf)
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#define AMCFGR_EL0_N_SHIFT U(0)
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#define AMCFGR_EL0_N_MASK U(0xff)
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/* AMCGCR_EL0 definitions */
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#define AMCGCR_EL0_CG1NC_SHIFT U(8)
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#define AMCGCR_EL0_CG1NC_LENGTH U(8)
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#define AMCGCR_EL0_CG1NC_MASK U(0xff)
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/* MPAM register definitions */
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@ -482,7 +482,8 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
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DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
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DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,13 +10,14 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include <platform_def.h>
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#include <lib/cassert.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* All group 0 counters */
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#define AMU_GROUP0_COUNTERS_MASK U(0xf)
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#define AMU_GROUP0_NR_COUNTERS U(4)
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#ifdef PLAT_AMU_GROUP1_COUNTERS_MASK
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#define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK
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@ -24,25 +25,67 @@
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#define AMU_GROUP1_COUNTERS_MASK U(0)
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#endif
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#ifdef PLAT_AMU_GROUP1_NR_COUNTERS
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#define AMU_GROUP1_NR_COUNTERS PLAT_AMU_GROUP1_NR_COUNTERS
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/* Calculate number of group 1 counters */
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#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15))
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#define AMU_GROUP1_NR_COUNTERS 16U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14))
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#define AMU_GROUP1_NR_COUNTERS 15U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13))
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#define AMU_GROUP1_NR_COUNTERS 14U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12))
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#define AMU_GROUP1_NR_COUNTERS 13U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11))
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#define AMU_GROUP1_NR_COUNTERS 12U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10))
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#define AMU_GROUP1_NR_COUNTERS 11U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9))
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#define AMU_GROUP1_NR_COUNTERS 10U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8))
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#define AMU_GROUP1_NR_COUNTERS 9U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7))
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#define AMU_GROUP1_NR_COUNTERS 8U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6))
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#define AMU_GROUP1_NR_COUNTERS 7U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5))
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#define AMU_GROUP1_NR_COUNTERS 6U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4))
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#define AMU_GROUP1_NR_COUNTERS 5U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3))
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#define AMU_GROUP1_NR_COUNTERS 4U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2))
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#define AMU_GROUP1_NR_COUNTERS 3U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1))
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#define AMU_GROUP1_NR_COUNTERS 2U
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#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0))
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#define AMU_GROUP1_NR_COUNTERS 1U
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#else
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#define AMU_GROUP1_NR_COUNTERS U(0)
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#define AMU_GROUP1_NR_COUNTERS 0U
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#endif
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CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
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CASSERT(AMU_GROUP1_NR_COUNTERS <= 16, invalid_amu_group1_nr_counters);
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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#if AMU_GROUP1_NR_COUNTERS
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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#endif
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};
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bool amu_supported(void);
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void amu_enable(bool el2_unused);
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/* Group 0 configuration helpers */
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uint64_t amu_group0_cnt_read(int idx);
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void amu_group0_cnt_write(int idx, uint64_t val);
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uint64_t amu_group0_cnt_read(unsigned int idx);
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void amu_group0_cnt_write(unsigned int idx, uint64_t val);
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#if AMU_GROUP1_NR_COUNTERS
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bool amu_group1_supported(void);
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/* Group 1 configuration helpers */
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uint64_t amu_group1_cnt_read(int idx);
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void amu_group1_cnt_write(int idx, uint64_t val);
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void amu_group1_set_evtype(int idx, unsigned int val);
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uint64_t amu_group1_cnt_read(unsigned int idx);
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void amu_group1_cnt_write(unsigned int idx, uint64_t val);
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void amu_group1_set_evtype(unsigned int idx, unsigned int val);
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#endif
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#endif /* AMU_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,11 +9,11 @@
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#include <stdint.h>
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uint64_t amu_group0_cnt_read_internal(int idx);
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void amu_group0_cnt_write_internal(int idx, uint64_t val);
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uint64_t amu_group0_cnt_read_internal(unsigned int idx);
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void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
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uint64_t amu_group1_cnt_read_internal(int idx);
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void amu_group1_cnt_write_internal(int idx, uint64_t val);
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void amu_group1_set_evtype_internal(int idx, unsigned int val);
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uint64_t amu_group1_cnt_read_internal(unsigned int idx);
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void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
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void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
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#endif /* AMU_PRIVATE_H */
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@ -1,39 +1,74 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub_events.h>
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#include <lib/extensions/amu.h>
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#include <lib/extensions/amu_private.h>
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#include <plat/common/platform.h>
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#define AMU_GROUP0_NR_COUNTERS 4
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struct amu_ctx {
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uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
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uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */
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bool amu_supported(void)
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{
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uint64_t features;
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uint32_t features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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return (features & ID_PFR0_AMU_MASK) == 1U;
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features &= ID_PFR0_AMU_MASK;
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return ((features == 1U) || (features == 2U));
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Check if group 1 counters is implemented */
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bool amu_group1_supported(void)
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{
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uint32_t features = read_amcfgr() >> AMCFGR_NCG_SHIFT;
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return (features & AMCFGR_NCG_MASK) == 1U;
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}
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#endif
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/*
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* Enable counters. This function is meant to be invoked
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* by the context management library before exiting from EL3.
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*/
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void amu_enable(bool el2_unused)
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{
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if (!amu_supported())
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if (!amu_supported()) {
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INFO("AMU is not implemented\n");
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return;
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Check and set presence of group 1 counters */
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if (!amu_group1_supported()) {
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ERROR("AMU Counter Group 1 is not implemented\n");
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panic();
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}
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/* Check number of group 1 counters */
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uint32_t cnt_num = (read_amcgcr() >> AMCGCR_CG1NC_SHIFT) &
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AMCGCR_CG1NC_MASK;
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VERBOSE("%s%u. %s%u\n",
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"Number of AMU Group 1 Counters ", cnt_num,
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"Requested number ", AMU_GROUP1_NR_COUNTERS);
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if (cnt_num < AMU_GROUP1_NR_COUNTERS) {
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ERROR("%s%u is less than %s%u\n",
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"Number of AMU Group 1 Counters ", cnt_num,
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"Requested number ", AMU_GROUP1_NR_COUNTERS);
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panic();
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}
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#endif
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if (el2_unused) {
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uint64_t v;
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@ -49,112 +84,156 @@ void amu_enable(bool el2_unused)
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/* Enable group 0 counters */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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#if AMU_GROUP1_NR_COUNTERS
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/* Enable group 1 counters */
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write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
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#endif
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(int idx)
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uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(amu_supported());
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assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val`. */
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void amu_group0_cnt_write(int idx, uint64_t val)
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/* Write the group 0 counter identified by the given `idx` with `val` */
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void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_supported());
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assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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/* Read the group 1 counter identified by the given `idx`. */
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uint64_t amu_group1_cnt_read(int idx)
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#if AMU_GROUP1_NR_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(amu_supported());
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assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val`. */
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void amu_group1_cnt_write(int idx, uint64_t val)
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/* Write the group 1 counter identified by the given `idx` with `val` */
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void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_supported());
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assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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void amu_group1_set_evtype(int idx, unsigned int val)
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/*
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* Program the event type register for the given `idx` with
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* the event number `val`
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*/
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void amu_group1_set_evtype(unsigned int idx, unsigned int val)
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{
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assert(amu_supported());
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assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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#endif /* AMU_GROUP1_NR_COUNTERS */
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static void *amu_context_save(const void *arg)
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{
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struct amu_ctx *ctx;
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int i;
|
||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
unsigned int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (!amu_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
|
||||
/* Assert that group 0 counter configuration is what we expect */
|
||||
assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK &&
|
||||
read_amcntenset1() == AMU_GROUP1_COUNTERS_MASK);
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
if (!amu_group1_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
#endif
|
||||
/* Assert that group 0/1 counter configuration is what we expect */
|
||||
assert(read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
assert(read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
/*
|
||||
* Disable group 0 counters to avoid other observers like SCP sampling
|
||||
* Disable group 0/1 counters to avoid other observers like SCP sampling
|
||||
* counter values from the future via the memory mapped view.
|
||||
*/
|
||||
write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
isb();
|
||||
|
||||
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
|
||||
/* Save all group 0 counters */
|
||||
for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
|
||||
ctx->group0_cnts[i] = amu_group0_cnt_read(i);
|
||||
}
|
||||
|
||||
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
|
||||
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Save group 1 counters */
|
||||
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
|
||||
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
|
||||
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return (void *)0;
|
||||
}
|
||||
|
||||
static void *amu_context_restore(const void *arg)
|
||||
{
|
||||
struct amu_ctx *ctx;
|
||||
int i;
|
||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
unsigned int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (!amu_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
if (!amu_group1_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
#endif
|
||||
/* Counters were disabled in `amu_context_save()` */
|
||||
assert((read_amcntenset0() == 0U) && (read_amcntenset1() == 0U));
|
||||
assert(read_amcntenset0_el0() == 0U);
|
||||
|
||||
/* Restore group 0 counters */
|
||||
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
assert(read_amcntenset1_el0() == 0U);
|
||||
#endif
|
||||
|
||||
/* Restore all group 0 counters */
|
||||
for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
|
||||
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
|
||||
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
|
||||
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
|
||||
}
|
||||
|
||||
/* Enable group 0 counters */
|
||||
/* Restore group 0 counter configuration */
|
||||
write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
/* Enable group 1 counters */
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Restore group 1 counters */
|
||||
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
|
||||
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
|
||||
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore group 1 counter configuration */
|
||||
write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
|
||||
return (void *)0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -9,38 +9,68 @@
|
|||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
|
||||
#include <lib/el3_runtime/pubsub_events.h>
|
||||
#include <lib/extensions/amu.h>
|
||||
#include <lib/extensions/amu_private.h>
|
||||
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#define AMU_GROUP0_NR_COUNTERS 4
|
||||
|
||||
struct amu_ctx {
|
||||
uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
|
||||
uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
|
||||
};
|
||||
|
||||
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
|
||||
|
||||
/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */
|
||||
bool amu_supported(void)
|
||||
{
|
||||
uint64_t features;
|
||||
uint64_t features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
|
||||
|
||||
features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
|
||||
return (features & ID_AA64PFR0_AMU_MASK) == 1U;
|
||||
features &= ID_AA64PFR0_AMU_MASK;
|
||||
return ((features == 1U) || (features == 2U));
|
||||
}
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Check if group 1 counters is implemented */
|
||||
bool amu_group1_supported(void)
|
||||
{
|
||||
uint64_t features = read_amcfgr_el0() >> AMCFGR_EL0_NCG_SHIFT;
|
||||
|
||||
return (features & AMCFGR_EL0_NCG_MASK) == 1U;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable counters. This function is meant to be invoked
|
||||
* Enable counters. This function is meant to be invoked
|
||||
* by the context management library before exiting from EL3.
|
||||
*/
|
||||
void amu_enable(bool el2_unused)
|
||||
{
|
||||
uint64_t v;
|
||||
|
||||
if (!amu_supported())
|
||||
if (!amu_supported()) {
|
||||
INFO("AMU is not implemented\n");
|
||||
return;
|
||||
}
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Check and set presence of group 1 counters */
|
||||
if (!amu_group1_supported()) {
|
||||
ERROR("AMU Counter Group 1 is not implemented\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Check number of group 1 counters */
|
||||
uint64_t cnt_num = (read_amcgcr_el0() >> AMCGCR_EL0_CG1NC_SHIFT) &
|
||||
AMCGCR_EL0_CG1NC_MASK;
|
||||
VERBOSE("%s%llu. %s%u\n",
|
||||
"Number of AMU Group 1 Counters ", cnt_num,
|
||||
"Requested number ", AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
if (cnt_num < AMU_GROUP1_NR_COUNTERS) {
|
||||
ERROR("%s%llu is less than %s%u\n",
|
||||
"Number of AMU Group 1 Counters ", cnt_num,
|
||||
"Requested number ", AMU_GROUP1_NR_COUNTERS);
|
||||
panic();
|
||||
}
|
||||
#endif
|
||||
|
||||
if (el2_unused) {
|
||||
/*
|
||||
|
|
@ -62,43 +92,49 @@ void amu_enable(bool el2_unused)
|
|||
|
||||
/* Enable group 0 counters */
|
||||
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Enable group 1 counters */
|
||||
write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Read the group 0 counter identified by the given `idx`. */
|
||||
uint64_t amu_group0_cnt_read(int idx)
|
||||
uint64_t amu_group0_cnt_read(unsigned int idx)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
|
||||
assert(idx < AMU_GROUP0_NR_COUNTERS);
|
||||
|
||||
return amu_group0_cnt_read_internal(idx);
|
||||
}
|
||||
|
||||
/* Write the group 0 counter identified by the given `idx` with `val`. */
|
||||
void amu_group0_cnt_write(int idx, uint64_t val)
|
||||
/* Write the group 0 counter identified by the given `idx` with `val` */
|
||||
void amu_group0_cnt_write(unsigned int idx, uint64_t val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert((idx >= 0) && (idx < AMU_GROUP0_NR_COUNTERS));
|
||||
assert(idx < AMU_GROUP0_NR_COUNTERS);
|
||||
|
||||
amu_group0_cnt_write_internal(idx, val);
|
||||
isb();
|
||||
}
|
||||
|
||||
/* Read the group 1 counter identified by the given `idx`. */
|
||||
uint64_t amu_group1_cnt_read(int idx)
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Read the group 1 counter identified by the given `idx` */
|
||||
uint64_t amu_group1_cnt_read(unsigned int idx)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
|
||||
assert(amu_group1_supported());
|
||||
assert(idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
return amu_group1_cnt_read_internal(idx);
|
||||
}
|
||||
|
||||
/* Write the group 1 counter identified by the given `idx` with `val`. */
|
||||
void amu_group1_cnt_write(int idx, uint64_t val)
|
||||
/* Write the group 1 counter identified by the given `idx` with `val` */
|
||||
void amu_group1_cnt_write(unsigned int idx, uint64_t val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
|
||||
assert(amu_group1_supported());
|
||||
assert(idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
amu_group1_cnt_write_internal(idx, val);
|
||||
isb();
|
||||
|
|
@ -106,78 +142,106 @@ void amu_group1_cnt_write(int idx, uint64_t val)
|
|||
|
||||
/*
|
||||
* Program the event type register for the given `idx` with
|
||||
* the event number `val`.
|
||||
* the event number `val`
|
||||
*/
|
||||
void amu_group1_set_evtype(int idx, unsigned int val)
|
||||
void amu_group1_set_evtype(unsigned int idx, unsigned int val)
|
||||
{
|
||||
assert(amu_supported());
|
||||
assert((idx >= 0) && (idx < AMU_GROUP1_NR_COUNTERS));
|
||||
assert(amu_group1_supported());
|
||||
assert(idx < AMU_GROUP1_NR_COUNTERS);
|
||||
|
||||
amu_group1_set_evtype_internal(idx, val);
|
||||
isb();
|
||||
}
|
||||
#endif /* AMU_GROUP1_NR_COUNTERS */
|
||||
|
||||
static void *amu_context_save(const void *arg)
|
||||
{
|
||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (!amu_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
if (!amu_group1_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
#endif
|
||||
/* Assert that group 0/1 counter configuration is what we expect */
|
||||
assert((read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK) &&
|
||||
(read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK));
|
||||
|
||||
assert(((sizeof(int) * 8) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
|
||||
<= AMU_GROUP1_NR_COUNTERS);
|
||||
assert(read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
assert(read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
/*
|
||||
* Disable group 0/1 counters to avoid other observers like SCP sampling
|
||||
* counter values from the future via the memory mapped view.
|
||||
*/
|
||||
write_amcntenclr0_el0(AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
write_amcntenclr1_el0(AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
isb();
|
||||
|
||||
/* Save group 0 counters */
|
||||
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
|
||||
/* Save all group 0 counters */
|
||||
for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
|
||||
ctx->group0_cnts[i] = amu_group0_cnt_read(i);
|
||||
}
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Save group 1 counters */
|
||||
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
|
||||
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
|
||||
|
||||
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
|
||||
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
|
||||
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return (void *)0;
|
||||
}
|
||||
|
||||
static void *amu_context_restore(const void *arg)
|
||||
{
|
||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
if (!amu_supported())
|
||||
if (!amu_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
if (!amu_group1_supported()) {
|
||||
return (void *)-1;
|
||||
}
|
||||
#endif
|
||||
/* Counters were disabled in `amu_context_save()` */
|
||||
assert((read_amcntenset0_el0() == 0U) && (read_amcntenset1_el0() == 0U));
|
||||
assert(read_amcntenset0_el0() == 0U);
|
||||
|
||||
assert(((sizeof(int) * 8U) - __builtin_clz(AMU_GROUP1_COUNTERS_MASK))
|
||||
<= AMU_GROUP1_NR_COUNTERS);
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
assert(read_amcntenset1_el0() == 0U);
|
||||
#endif
|
||||
|
||||
/* Restore group 0 counters */
|
||||
for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
|
||||
if ((AMU_GROUP0_COUNTERS_MASK & (1U << i)) != 0U)
|
||||
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
|
||||
/* Restore all group 0 counters */
|
||||
for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
|
||||
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
|
||||
}
|
||||
|
||||
/* Restore group 1 counters */
|
||||
for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
|
||||
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U)
|
||||
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
|
||||
|
||||
/* Restore group 0/1 counter configuration */
|
||||
/* Restore group 0 counter configuration */
|
||||
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
|
||||
|
||||
#if AMU_GROUP1_NR_COUNTERS
|
||||
/* Restore group 1 counters */
|
||||
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
|
||||
if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
|
||||
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore group 1 counter configuration */
|
||||
write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
|
||||
#endif
|
||||
|
||||
return (void *)0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue