andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge "board/rddanielxlr: add support for rd-daniel config-xlr platform" into integration

This commit is contained in:
Manish Pandey 2020-04-23 20:35:48 +00:00 committed by TrustedFirmware Code Review
parent 9c1a6f4e71 5a726a5dcc
commit f4701a776d
8 changed files with 399 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <export/common/tbbr/tbbr_img_def_exp.h>
/dts-v1/;
/ {
dtb-registry {
compatible = "arm,dyn_cfg-dtb_registry";
/* tb_fw_config is temporarily contained on this dtb */
tb_fw-config {
load-address = <0x0 0x4001010>;
max-size = <0x200>;
id = <TB_FW_CONFIG_ID>;
};
nt_fw-config {
load-address = <0x0 0xFEF00000>;
max-size = <0x0100000>;
id = <NT_FW_CONFIG_ID>;
};
};
tb_fw-config {
compatible = "arm,tb_fw";
/* Disable authentication for development */
disable_auth = <0x0>;
/*
* The following two entries are placeholders for Mbed TLS
* heap information. The default values don't matter since
* they will be overwritten by BL1.
* In case of having shared Mbed TLS heap between BL1 and BL2,
* BL1 will populate these two properties with the respective
* info about the shared heap. This info will be available for
* BL2 in order to locate and re-use the heap.
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
};

22
plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,rd-daniel-xlr";
/*
* Place holder for system-id node with default values. The
* value of platform-id and config-id will be set to the
* correct values during the BL2 stage of boot.
*/
system-id {
platform-id = <0x0>;
config-id = <0x0>;
multi-chip-mode = <0x0>;
};
};

37
plat/arm/board/rddanielxlr/include/platform_def.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_base_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(4)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
/* Physical and virtual address space limits for MMU in AARCH64 mode */
#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
CSS_SGI_CHIP_COUNT)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
#endif /* PLATFORM_DEF_H */

57
plat/arm/board/rddanielxlr/platform.mk Normal file
View File

@ -0,0 +1,57 @@
# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Enable GICv4 extension with multichip driver
GIC_ENABLE_V4_EXTN := 1
GICV3_IMPL_GIC600_MULTICHIP := 1
include plat/arm/css/sgi/sgi-common.mk
RDDANIELXLR_BASE = plat/arm/board/rddanielxlr
PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIELXLR_BASE}/rddanielxlr_err.c
BL2_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
${RDDANIELXLR_BASE}/rddanielxlr_security.c \
${RDDANIELXLR_BASE}/rddanielxlr_err.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
${RDDANIELXLR_BASE}/rddanielxlr_topology.c \
drivers/cfi/v2m/v2m_flash.c \
drivers/arm/gic/v3/gic600_multichip.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
# Enable dynamic addition of MMAP regions in BL31
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
$(eval $(call CREATE_SEQ,SEQ,4))
ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
$(error "Chip count for RD-Daniel Config-XLR should be either $(SEQ) \
currently it is set to ${CSS_SGI_CHIP_COUNT}.")
endif
FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0

17
plat/arm/board/rddanielxlr/rddanielxlr_err.c Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* rddanielxlr error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
while (true) {
wfi();
}
}

131
plat/arm/board/rddanielxlr/rddanielxlr_plat.c Normal file
View File

@ -0,0 +1,131 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <sgi_base_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)
static const mmap_region_t rddanielxlr_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
#if (CSS_SGI_CHIP_COUNT > 2)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3)
#endif
};
static struct gic600_multichip_data rddanielxlr_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
.chip_addrs = {
PLAT_ARM_GICD_BASE >> 16,
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
#if (CSS_SGI_CHIP_COUNT > 2)
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
#endif
},
.spi_ids = {
{32, 255},
{0, 0},
#if (CSS_SGI_CHIP_COUNT > 2)
{0, 0},
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
{0, 0},
#endif
}
};
static uintptr_t rddanielxlr_multichip_gicr_frames[] = {
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
/* Chip 1's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
#if (CSS_SGI_CHIP_COUNT > 2)
/* Chip 2's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
/* Chip 3's GICR BASE */
PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
#endif
UL(0) /* Zero Termination */
};
#endif /* IMAGE_BL31 */
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
& SID_SYSTEM_ID_PART_NUM_MASK;
}
unsigned int plat_arm_sgi_get_config_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
}
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
}
/*
* bl31_platform_setup_function is guarded by IMAGE_BL31 macro because
* PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
* for other stages.
*/
#if defined(IMAGE_BL31)
void bl31_platform_setup(void)
{
int ret;
unsigned int i;
if ((plat_arm_sgi_get_multi_chip_mode() == 0) &&
(CSS_SGI_CHIP_COUNT > 1)) {
ERROR("Chip Count is set to %u but multi-chip mode is not "
"enabled\n", CSS_SGI_CHIP_COUNT);
panic();
} else if ((plat_arm_sgi_get_multi_chip_mode() == 1) &&
(CSS_SGI_CHIP_COUNT > 1)) {
INFO("Enabling support for multi-chip in RD-Daniel Cfg-XLR\n");
for (i = 0; i < ARRAY_SIZE(rddanielxlr_dynamic_mmap); i++) {
ret = mmap_add_dynamic_region(
rddanielxlr_dynamic_mmap[i].base_pa,
rddanielxlr_dynamic_mmap[i].base_va,
rddanielxlr_dynamic_mmap[i].size,
rddanielxlr_dynamic_mmap[i].attr);
if (ret != 0) {
ERROR("Failed to add dynamic mmap entry "
"(ret=%d)\n", ret);
panic();
}
}
plat_arm_override_gicr_frames(
rddanielxlr_multichip_gicr_frames);
gic600_multichip_init(&rddanielxlr_multichip_data);
}
sgi_bl31_common_platform_setup();
}
#endif /* IMAGE_BL31 */

10
plat/arm/board/rddanielxlr/rddanielxlr_security.c Normal file
View File

@ -0,0 +1,10 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
}

78
plat/arm/board/rddanielxlr/rddanielxlr_topology.c Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
#include <sgi_variant.h>
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_daniel_xlr_pd_tree_desc_multi_chip[] = {
((PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT)),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#if (CSS_SGI_CHIP_COUNT > 1)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER
#endif
};
/*******************************************************************************
* This function returns the topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
if (plat_arm_sgi_get_multi_chip_mode() == 1)
return rd_daniel_xlr_pd_tree_desc_multi_chip;
panic();
}
/*******************************************************************************
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
#if (CSS_SGI_CHIP_COUNT > 1)
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 2)
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
#endif
#if (CSS_SGI_CHIP_COUNT > 3)
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
#endif
};