fix(intel): make FPGA memory configurations platform specific
Define FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in platform-specific header. This is due to different allocated sizes between platforms. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76
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@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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/* Register Mapping */
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/* Register Mapping */
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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@ -56,10 +56,6 @@
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SYSMGR_ECC_DDR0_MASK |\
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SYSMGR_ECC_DDR0_MASK |\
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SYSMGR_ECC_DDR1_MASK)
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SYSMGR_ECC_DDR1_MASK)
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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/* SMC function IDs for SiP Service queries */
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/* SMC function IDs for SiP Service queries */
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_CALL_COUNT 0x8200ff00
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#define SIP_SVC_UID 0x8200ff01
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#define SIP_SVC_UID 0x8200ff01
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/*
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/*
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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/* Register Mapping */
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/* Register Mapping */
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#define SOCFPGA_MMC_REG_BASE U(0xff808000)
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#define SOCFPGA_MMC_REG_BASE U(0xff808000)
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/*
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000
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/* Register Mapping */
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/* Register Mapping */
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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