plat: ti: k3: board: Lets cast our macros
Lets cast our macros to the right types and reduce a few MISRA warnings. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c
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@ -19,14 +19,14 @@
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* It may need to be increased if BL31 grows in size.
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* It may need to be increased if BL31 grows in size.
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*/
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*/
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#define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */
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#define SEC_SRAM_BASE UL(0x70000000) /* Base of MSMC SRAM */
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#define SEC_SRAM_SIZE 0x00020000 /* 128k */
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#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_PROC_START_ID 32
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#define PLAT_PROC_START_ID U(32)
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#define PLAT_PROC_DEVICE_START_ID 202
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#define PLAT_PROC_DEVICE_START_ID U(202)
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#define PLAT_CLUSTER_DEVICE_START_ID 198
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#define PLAT_CLUSTER_DEVICE_START_ID U(198)
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#endif /* BOARD_DEF_H */
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#endif /* BOARD_DEF_H */
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@ -21,14 +21,14 @@
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* Current computation assumes data structures necessary for GIC and ARM for
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* Current computation assumes data structures necessary for GIC and ARM for
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* a single cluster of 4 processor.
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* a single cluster of 4 processor.
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*/
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*/
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#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */
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#define SEC_SRAM_BASE UL(0x70000000) /* Base of SRAM */
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#define SEC_SRAM_SIZE 0x0001c000 /* 112k */
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#define SEC_SRAM_SIZE UL(0x0001c000) /* 112k */
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_PROC_START_ID 32
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#define PLAT_PROC_START_ID U(32)
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#define PLAT_PROC_DEVICE_START_ID 135
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#define PLAT_PROC_DEVICE_START_ID U(135)
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#define PLAT_CLUSTER_DEVICE_START_ID 134
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#define PLAT_CLUSTER_DEVICE_START_ID U(134)
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#endif /* BOARD_DEF_H */
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#endif /* BOARD_DEF_H */
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